Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Public
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2. Intel® -Specific Errata for the Intel® Stratix® 10 DX Devices

This section lists the errata that apply to the Intel® Stratix® 10 DX devices. Each listed erratum has an associated status that identifies any planned fixes.

Table 1.  Device Issues
Issue Affected Devices Planned Fix
FPGA
Device Power Supply, Core and I/O
M20K Simple Quad-Port Mode Support
  • Intel® Stratix® 10 Devices with Fixed Voltage:
    • 1SxxxxxxxxxxE2Lx
    • 1SxxxxxxxxxxE3Xx
    • 1SxxxxxxxxxxI2Lx
    • 1SxxxxxxxxxxI3Xx
    • 1SxxxxxxxxxxC2Lx
  • Intel® Stratix® 10 Devices with Industrial Grade Smart VID:
    • 1SxxxxxxxxxxI1Vx
    • 1SxxxxxxxxxxI2Vx
    • 1SxxxxxxxxxxI3Vx
No planned fix
P-Tile
Root Port Legacy Interrupt Status register INTx is stuck HIGH
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
TLP Bypass Error Status Register may Report Receiver Errors
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
PCIe CV and PTC Tests in the PCI-SIG Compliance Test Suite may Fail
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
Fixed in the Intel® Quartus® Prime Pro Edition software version 21.3
Returning Incorrect Function Number
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
Incorrect Return Value for Power Management Register
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
Fixed in the Intel® Quartus® Prime Pro Edition software version 20.1
Register Implementation while using the SR-IOV Feature
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
Register Implementation while using the Multi-function Feature
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
Unsuccessful TX Equalization
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
Link Does Not Degrade With Corrupt Lanes
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100
No planned fix
Warm Reset or PERST Assertion Clears the Sticky Registers
  • Intel® Stratix® 10 DX 2800
No planned fix
Hard Processor System
HPS Stops on the First Read Request to SDRAM Intel® Stratix® 10 DX 1100 No planned fix
Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition Intel® Stratix® 10 DX 1100 No planned fix