3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail
The Cortex-A53 MPCore* processor implements an internal exclusive monitor to manage load-exclusive, store-exclusive, and clear-exclusive instructions. Because of this erratum, a load-exclusive instruction to cacheable memory may set the monitor to the exclusive state when the processor does not have exclusive access to the line. A subsequent store-exclusive instruction may pass when it should fail.
This erratum affects all load-exclusive and store-exclusive instructions, including load-acquire exclusive and store-release exclusive instructions.
- A core executes a store to memory that is marked as both inner-writeback and outer-writeback.
- The store is not a store-exclusive (or a store-release exclusive) or a store-release instruction.
- The store is not followed by a DMB SY or DSB.
- The store misses in the L1 data cache.
- The store does not trigger a linefill. This requires one or more of the following to be true:
- The core is in read-allocate mode
- The memory is marked as no-write-allocate
- The memory is marked as transient
- The store is a STNP instruction
- The store is triggered by a DC ZVA instruction
- The core starts a linefill to the same address as the store. The linefill is started for one of the following:
- A PRFM, PLD, or PLDW instruction
- An automatic data prefetch
- A pagewalk
- The core executes a load-exclusive (or a load-acquire exclusive) instruction to the same address as the store
- The store data is forwarded to the load-exclusive instruction
- If a core starts a linefill to the same address as the store, the load-exclusive instruction retires before the linefill is serialized.
If the above conditions are met then the Cortex-A53 MPCore* processor may set the internal exclusive monitor. This behavior is incorrect because the processor is not guaranteed to have exclusive access to the line. If another master executes a load-exclusive instruction to the same address then both masters may gain access to an exclusive region of code at the same time.
The only workaround is to avoid the conditions described above. Disabling read-allocate mode by setting CPUACTLR.RADIS to 0x3 degrades write-stream performance. Therefore, the preferred workaround is to use an appropriate store-exclusive (or a store-release exclusive) or a store-release instruction or DMB instruction.