Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Document Table of Contents
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2.3.5. Incorrect Return Value for Power Management Register


While using the Intel FPGA P-Tile Hard IP for PCIe, the Power Management Control and Status Register (offset 0x04Ch bit [3]: No_Soft_Reset) returns a value of 1’b0 instead of value of 1’b1. As a result, the software expects the Intel FPGA P-Tile Hard IP for PCIe to reset the configuration space during transition from D3 HOT state to D0 state.

Impacted Modes

  • Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe in Endpoint, Root Port, and TLP Bypass modes
  • Intel FPGA P-Tile Avalon® Memory-Mapped Interface IP for PCIe in Endpoint and Root Port modes




  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: Fixed in the Intel® Quartus® Prime Pro Edition software version 20.1.