Intel® Stratix® 10 DX Device Errata

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ID 683249
Date 11/01/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® -Specific Errata for the Intel® Stratix® 10 DX Devices 3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata 4. Document Revision History for Intel® Stratix® 10 DX Device Errata
2. Intel® -Specific Errata for the Intel® Stratix® 10 DX Devices x
2.1. FPGA 2.2. Device Power Supply, Core and I/O 2.3. P-Tile 2.4. Hard Processor System
2.2. Device Power Supply, Core and I/O x
2.2.1. M20K Simple Quad-Port Mode Support
2.3. P-Tile x
2.3.1. Root Port Legacy Interrupt Status register INTx is stuck HIGH 2.3.2. TLP Bypass Error Status Register may Report Receiver Errors 2.3.3. PCIe CV and PTC Tests in the PCI-SIG Compliance Test Suite may Fail 2.3.4. Returning Incorrect Function Number 2.3.5. Incorrect Return Value for Power Management Register 2.3.6. Register Implementation while using the SR-IOV Feature 2.3.7. Register Implementation while using the Multi-function Feature Description Impacted Modes Workaround Status 2.3.8. Unsuccessful TX Equalization 2.3.9. Link Does Not Degrade With Corrupt Lanes 2.3.10. Warm Reset or PERST Assertion Clears the Sticky Registers
2.4. Hard Processor System x
2.4.1. HPS Stops on the First Read Request to SDRAM 2.4.2. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Intel® -Specific Errata for the Intel® Stratix® 10 DX Devices
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata
4. Document Revision History for Intel® Stratix® 10 DX Device Errata

2.3.7. Register Implementation while using the Multi-function Feature

Description

While using the Intel FPGA P-Tile Hard IP for PCIe:
  • When the multi-function feature is enabled, the PCIe device status register (offset 0x07Ah bit [5]: Transactions pending bit) for each of the virtual functions (VF) is implemented as a Write-1-to-Clear status register (RW1C). According to the PCIe Base specification revision 4.0 version 1.0, this register must be implemented as read-only (RO) when multi-function feature is enabled.

These issues do not cause functional failure.

Impacted Modes

  • Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe in Endpoint mode
  • Intel FPGA P-Tile Avalon® Memory-Mapped Interface IP for PCIe in Endpoint mode

Workaround

The application logic can use Configuration Intercept Interface (CII) or Direct User Avalon Memory-Mapped Interface to modify the configuration accesses to this register.

Using the Direct User Avalon Memory-Mapped Interface:

The application logic must implement a tracking logic for any pending upstream memory read (MRd) completion. After the last pending MRd completion is received, refer to the Using Direct User Avalon® Memory-Mapped Interface (Byte Access) to clear the Transactions pending bit in the Device Status register. The following sequence is an example for VF3 in PF0.

  1. Application logic programs the User Avalon® memory-mapped interface Port Configuration Register (Offset 0x10406A, addressing the third byte of the register) with 0x0A (vf_num[28:18] = 2, vf _select[17] = 1, vsec[0] = 0).
  2. Application logic sets the hip_reconfig_addr_i[20:0] with 0x7A which corresponds to the Device Status register within the VF PCI Express Capability Structure1 and performs a write 1 operation to the Transaction pending bit [5] by setting the hip_reconfig_writedata_i[7:0] to 0x20.

Figure 1. VF3 in PF0 Configuration Space Registers Access Timing Diagram

Status

Affects:
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: No planned fix.

1 For more details, refer to the PCIe Configuration Registers for Each Virtual Function
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