Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Document Table of Contents
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2.3.7. Register Implementation while using the Multi-function Feature


While using the Intel FPGA P-Tile Hard IP for PCIe:
  • When the multi-function feature is enabled, the PCIe device status register (offset 0x07Ah bit [5]: Transactions pending bit) for each of the virtual functions (VF) is implemented as a Write-1-to-Clear status register (RW1C). According to the PCIe Base specification revision 4.0 version 1.0, this register must be implemented as read-only (RO) when multi-function feature is enabled.

These issues do not cause functional failure.

Impacted Modes

  • Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe in Endpoint mode
  • Intel FPGA P-Tile Avalon® Memory-Mapped Interface IP for PCIe in Endpoint mode


The application logic can use Configuration Intercept Interface (CII) or Direct User Avalon Memory-Mapped Interface to modify the configuration accesses to this register.

Using the Direct User Avalon Memory-Mapped Interface:

The application logic must implement a tracking logic for any pending upstream memory read (MRd) completion. After the last pending MRd completion is received, refer to the Using Direct User Avalon® Memory-Mapped Interface (Byte Access) to clear the Transactions pending bit in the Device Status register. The following sequence is an example for VF3 in PF0.

  1. Application logic programs the User Avalon® memory-mapped interface Port Configuration Register (Offset 0x10406A, addressing the third byte of the register) with 0x0A (vf_num[28:18] = 2, vf _select[17] = 1, vsec[0] = 0).
  2. Application logic sets the hip_reconfig_addr_i[20:0] with 0x7A which corresponds to the Device Status register within the VF PCI Express Capability Structure1 and performs a write 1 operation to the Transaction pending bit [5] by setting the hip_reconfig_writedata_i[7:0] to 0x20.

Figure 1. VF3 in PF0 Configuration Space Registers Access Timing Diagram


  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: No planned fix.