Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Public
Document Table of Contents
Give Feedback

2.3.9. Link Does Not Degrade With Corrupt Lanes

Description

When using P-Tile Intel FPGA IP for PCIe* , if one or more lanes is corrupted (for example: faulty connection in the TX/RX pin) or not connected, the link may not downgrade as expected. For example, if lane 3 and 8 of a x16 link are not connected, the link may downgrade to x2 (active lanes 0-1), instead of x4 (active lanes 12-15).​

Ensure that the P-Tile PCIe* IP link width is configured according to your board implementation.​

Workaround

None.

Status

Affects:
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: No planned fix.