Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 12/16/2019
Public
Document Table of Contents
Document Table of Contents
1. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Combining Design Block Reuse and Incremental Block-Based Compilation 1.8. Setting-Up Team-Based Designs 1.9. Bottom-Up Design Considerations 1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.11. Block-Based Design Flows Revision History 1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
1.2. Block-Based Design Overview
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview
1.2.1.1. Design Block Reuse Examples
1.2.2. Incremental Block-Based Compilation Overview
1.2.2.1. Incremental Block-Based Compilation Examples
1.3. Design Methodologies Overview
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Design Partition Guidelines 1.4.3. Partition Snapshot Preservation and Reuse 1.4.4. Creating Design Partitions
1.5. Design Block Reuse Flows
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow
1.6.1. Incremental Timing Closure 1.6.2. Design Abstraction
1.6.1. Incremental Timing Closure
1.6.1.1. Incremental Timing Closure Recommendations and Limitations
1.6.2. Design Abstraction
1.6.2.1. Empty Partition Clock Source Preservation
1.8. Setting-Up Team-Based Designs
1.8.1. Creating a Top-Level Project for a Team-Based Design
1.8.1. Creating a Top-Level Project for a Team-Based Design
1.8.1.1. Prepare a Design Partition for Project Integration
1. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

1.5.2.1. Step 1: Developer: Create a Reserved Core Partition

To export and reuse the root partition, the Developer creates a reserved core partition for later core logic development in the Consumer project. The Compiler preserves post-fit results for the partition and reuses the post-fit netlist, if the netlist is available from previous compilation, and you make no partition changes requiring re-synthesis. Otherwise, the Compiler reuses the post-synthesis netlist if available, or resynthesizes the partition from source files.

To create a reserved core partition:

  1. Adapt the steps in Step 1: Developer: Create a Design Partition to create a reserved core partition.
  2. When defining the design partition, select Reserved Core for the partition Type. Ensure that all other partition options are set to the default values.
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