Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

Download PDF
ID 683247
Date 12/16/2019
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows x
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Combining Design Block Reuse and Incremental Block-Based Compilation 1.8. Setting-Up Team-Based Designs 1.9. Bottom-Up Design Considerations 1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.11. Block-Based Design Flows Revision History 1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
1.2. Block-Based Design Overview x
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview x
1.2.1.1. Design Block Reuse Examples
1.2.2. Incremental Block-Based Compilation Overview x
1.2.2.1. Incremental Block-Based Compilation Examples
1.3. Design Methodologies Overview x
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning x
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Design Partition Guidelines 1.4.3. Partition Snapshot Preservation and Reuse 1.4.4. Creating Design Partitions
1.5. Design Block Reuse Flows x
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions x
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions x
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information x
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow x
1.6.1. Incremental Timing Closure 1.6.2. Design Abstraction
1.6.1. Incremental Timing Closure x
1.6.1.1. Incremental Timing Closure Recommendations and Limitations
1.6.2. Design Abstraction x
1.6.2.1. Empty Partition Clock Source Preservation
1.8. Setting-Up Team-Based Designs x
1.8.1. Creating a Top-Level Project for a Team-Based Design
1.8.1. Creating a Top-Level Project for a Team-Based Design x
1.8.1.1. Prepare a Design Partition for Project Integration
1. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

1.6.1.1. Incremental Timing Closure Recommendations and Limitations

The following consideration and limitation apply to incremental timing closure:

Table 6.  Incremental Timing Closure Considerations and Limitations
Recommendation/Limitation Description
Recommendation 1 Set partition boundaries near major registered block interfaces, where there is minimal connectivity to external blocks, as these partition boundaries prevent cross-block optimization.
Recommendation 2 For incremental timing closure, there is no requirement to floorplan partitions with Logic Lock regions. However, use of Logic Lock regions can help the Compiler to achieve timing closure more quickly.
Recommendation 3 Lock down the source of the clock.
Recommendation 4 Lock down the region covered by the clock.
 
Limitation 1 The Compiler does not support partial periphery preservation. You can preserve only the full periphery (root_partition).
Limitation 2

Preserving a partition does not preserve any incoming and outgoing routing. The Compiler attributes routing that crosses partition boundaries to the common parent partition. More precisely, the Compiler determines routing based on the hierarchies that the net traverses in the RTL. Preserving parent partitions allows preservation of inter-partition routing.

Limitation 3

The Compiler generally routes global clocks from the top-level pins (in the root partition) to lower-level partitions. As a result, preserving a partition does not preserve these cross-partition global routes. When using incremental timing closure, the partitions you preserve can still be subject to slight timing variations due to difference in clock arrival times between compilations.

Limitation 4 The following factors can affect the timing of partitions you preserve:
  • The global clock network, which has a more significant impact for Intel® Stratix® 10 designs.
  • Cross talk. The impact is similar for Intel® Stratix® 10 and Intel® Arria® 10 designs.
  • Routing muxes.
Level Two Title