Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

Download
ID 683247
Date 12/16/2019
Public
Document Table of Contents

1.6.1.1. Incremental Timing Closure Recommendations and Limitations

The following consideration and limitation apply to incremental timing closure:

Table 6.  Incremental Timing Closure Considerations and Limitations
Recommendation/Limitation Description
Recommendation 1 Set partition boundaries near major registered block interfaces, where there is minimal connectivity to external blocks, as these partition boundaries prevent cross-block optimization.
Recommendation 2 For incremental timing closure, there is no requirement to floorplan partitions with Logic Lock regions. However, use of Logic Lock regions can help the Compiler to achieve timing closure more quickly.
Recommendation 3 Lock down the source of the clock.
Recommendation 4 Lock down the region covered by the clock.
 
Limitation 1 The Compiler does not support partial periphery preservation. You can preserve only the full periphery (root_partition).
Limitation 2

Preserving a partition does not preserve any incoming and outgoing routing. The Compiler attributes routing that crosses partition boundaries to the common parent partition. More precisely, the Compiler determines routing based on the hierarchies that the net traverses in the RTL. Preserving parent partitions allows preservation of inter-partition routing.

Limitation 3

The Compiler generally routes global clocks from the top-level pins (in the root partition) to lower-level partitions. As a result, preserving a partition does not preserve these cross-partition global routes. When using incremental timing closure, the partitions you preserve can still be subject to slight timing variations due to difference in clock arrival times between compilations.

Limitation 4 The following factors can affect the timing of partitions you preserve:
  • The global clock network, which has a more significant impact for Intel® Stratix® 10 designs.
  • Cross talk. The impact is similar for Intel® Stratix® 10 and Intel® Arria® 10 designs.
  • Routing muxes.

Did you find the information on this page useful?

Characters remaining:

Feedback Message