Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 12/16/2019
Public
Document Table of Contents

1.9. Bottom-Up Design Considerations

Consider the following recommendations and limitations when using a bottom-up design methodology

Recommendations and Limitations

Table 8.  Bottom-Up Design Recommendations and Limitations
Recommendation/Limitation Description
Recommendation 1 Define Logic Lock constraints that are Reserved, Core-Only, Fixed/Locked, with a specified Routing Region. While exporting partitions from a different project with a different top-level, generate the partitions with non-overlapping Logic Lock routing regions by setting the routing region to Fixed with expansion of 0.
 
Limitation 1 If you compile two partitions, in two different projects, with top_level_1.sv and top_level_2.sv, and reuse the partitions in a third project with top_level_3.sv, the Compiler cannot support two partitions with overlapping row clock regions. Apply Logic Lock region constraints in the Developer project to avoid two partitions occupying the same row clock region in the Consumer project. For example:
  1. From the Consumer project, determine the approximate placement of the two partitions. Choose the Logic Lock constraints for the two partitions such that there is no overlap of the row clock region.
  2. In the Developer project with top_level_1.sv, apply Logic Lock region constraints that the Consumer identifies for the first partition, followed by compilation and export of the partition at final snapshot.
  3. In the Developer project with top_level_2.sv, apply Logic Lock region constraints that the Consumer identifies for the second partition, followed by compilation and export of the partition at final snapshot.
  4. When reusing the exported partitions in the consumer project with top_level_3.sv, the partitions maintain the placement defined in the Developer projects using non-overlapping Logic Lock constraints.
Limitation 2

System-level design errors may not become apparent until late in the design cycle, which can require additional design iterations to resolve.

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