1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Combining Design Block Reuse and Incremental Block-Based Compilation 1.8. Setting-Up Team-Based Designs 1.9. Bottom-Up Design Considerations 1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.11. Block-Based Design Flows Revision History 1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
1.9. Bottom-Up Design Considerations
Consider the following recommendations and limitations when using a bottom-up design methodology
Recommendations and Limitations
|Recommendation 1||Define Logic Lock constraints that are Reserved, Core-Only, Fixed/Locked, with a specified Routing Region. While exporting partitions from a different project with a different top-level, generate the partitions with non-overlapping Logic Lock routing regions by setting the routing region to Fixed with expansion of 0.|
|Limitation 1||If you compile two partitions, in two different projects, with top_level_1.sv and top_level_2.sv, and reuse the partitions in a third project with top_level_3.sv, the Compiler cannot support two partitions with overlapping row clock regions. Apply Logic Lock region constraints in the Developer project to avoid two partitions occupying the same row clock region in the Consumer project. For example:
System-level design errors may not become apparent until late in the design cycle, which can require additional design iterations to resolve.
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