Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

ID 683247
Date 12/16/2019

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Document Table of Contents Incremental Block-Based Compilation Examples

You can use incremental block-based compilation to optimize a timing-critical partition or in Signal Tap debugging.
  • Optimize the results of one partition, without impacting the results of other design partitions that already meet their requirements.
  • Iteratively lock down the performance of one partition, and then move on to optimization of another partition.
  • Improve the predictability of results during iterations by preserving the partitions of the design that meet timing.
The following describe typical incremental block-based compilation examples:

Example 1: Optimizing a Timing-critical Partition

After performing a lengthy full compilation of a design with multiple partitions, the Timing Analyzer reports that the clock timing requirement is not met for a specific design partition.

You apply optimization techniques to the specific partition, such as raising the Placement Effort Multiplier option value. Because Placement Effort Multiplier optimization of the entire design requires significant compilation time, you can apply the optimization only to the partition in question.

Example 2: Design Debugging

After performing some early diagnostics, your design is not functioning as you expect. You decide to debug the design using the Signal Tap logic analyzer, but you want to ensure that adding Signal Tap logic to your design does not negatively affect completed portions of your design.

You preserve the compilation results and add Signal Tap to your design without recompiling the full design from source code. This flow improves the predictability of results during iterations whenever you need to add the logic analyzer to debug your design, or when you want to modify the configuration of the Signal Tap file (.stp) without modifying your design logic or placement.

Note: No recompilation of preserved partitions is only possible if the signals that you add for Signal Tap are from the logic you do not plan to preserve. Refer to AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board for considerations when using Signal Tap with block-based design flows.