Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

Download PDF
ID 683247
Date 12/16/2019
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows x
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Combining Design Block Reuse and Incremental Block-Based Compilation 1.8. Setting-Up Team-Based Designs 1.9. Bottom-Up Design Considerations 1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.11. Block-Based Design Flows Revision History 1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
1.2. Block-Based Design Overview x
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview x
1.2.1.1. Design Block Reuse Examples
1.2.2. Incremental Block-Based Compilation Overview x
1.2.2.1. Incremental Block-Based Compilation Examples Example 1: Optimizing a Timing-critical Partition Example 2: Design Debugging
1.3. Design Methodologies Overview x
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning x
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Design Partition Guidelines 1.4.3. Partition Snapshot Preservation and Reuse 1.4.4. Creating Design Partitions
1.5. Design Block Reuse Flows x
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions x
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions x
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information x
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow x
1.6.1. Incremental Timing Closure 1.6.2. Design Abstraction
1.6.1. Incremental Timing Closure x
1.6.1.1. Incremental Timing Closure Recommendations and Limitations
1.6.2. Design Abstraction x
1.6.2.1. Empty Partition Clock Source Preservation
1.8. Setting-Up Team-Based Designs x
1.8.1. Creating a Top-Level Project for a Team-Based Design
1.8.1. Creating a Top-Level Project for a Team-Based Design x
1.8.1.1. Prepare a Design Partition for Project Integration
1. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

1.2.2.1. Incremental Block-Based Compilation Examples

You can use incremental block-based compilation to optimize a timing-critical partition or in Signal Tap debugging.
  • Optimize the results of one partition, without impacting the results of other design partitions that already meet their requirements.
  • Iteratively lock down the performance of one partition, and then move on to optimization of another partition.
  • Improve the predictability of results during iterations by preserving the partitions of the design that meet timing.
The following describe typical incremental block-based compilation examples:

Example 1: Optimizing a Timing-critical Partition

After performing a lengthy full compilation of a design with multiple partitions, the Timing Analyzer reports that the clock timing requirement is not met for a specific design partition.

You apply optimization techniques to the specific partition, such as raising the Placement Effort Multiplier option value. Because Placement Effort Multiplier optimization of the entire design requires significant compilation time, you can apply the optimization only to the partition in question.

Example 2: Design Debugging

After performing some early diagnostics, your design is not functioning as you expect. You decide to debug the design using the Signal Tap logic analyzer, but you want to ensure that adding Signal Tap logic to your design does not negatively affect completed portions of your design.

You preserve the compilation results and add Signal Tap to your design without recompiling the full design from source code. This flow improves the predictability of results during iterations whenever you need to add the logic analyzer to debug your design, or when you want to modify the configuration of the Signal Tap file (.stp) without modifying your design logic or placement.

Note: No recompilation of preserved partitions is only possible if the signals that you add for Signal Tap are from the logic you do not plan to preserve. Refer to AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board for considerations when using Signal Tap with block-based design flows.
Related Information
Level Two Title