Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 12/16/2019
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Document Table of Contents
Document Table of Contents x
1. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows x
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Combining Design Block Reuse and Incremental Block-Based Compilation 1.8. Setting-Up Team-Based Designs 1.9. Bottom-Up Design Considerations 1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.11. Block-Based Design Flows Revision History 1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
1.2. Block-Based Design Overview x
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview x
1.2.1.1. Design Block Reuse Examples
1.2.2. Incremental Block-Based Compilation Overview x
1.2.2.1. Incremental Block-Based Compilation Examples
1.3. Design Methodologies Overview x
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning x
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Design Partition Guidelines 1.4.3. Partition Snapshot Preservation and Reuse 1.4.4. Creating Design Partitions
1.5. Design Block Reuse Flows x
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions x
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions x
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information x
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow x
1.6.1. Incremental Timing Closure 1.6.2. Design Abstraction
1.6.1. Incremental Timing Closure x
1.6.1.1. Incremental Timing Closure Recommendations and Limitations
1.6.2. Design Abstraction x
1.6.2.1. Empty Partition Clock Source Preservation
1.8. Setting-Up Team-Based Designs x
1.8.1. Creating a Top-Level Project for a Team-Based Design
1.8.1. Creating a Top-Level Project for a Team-Based Design x
1.8.1.1. Prepare a Design Partition for Project Integration
1. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

1.4.3. Partition Snapshot Preservation and Reuse

The Compiler generates a snapshot of compilation results, for each partition, at each stage of compilation. You can preserve and reuse partitions after synthesis or after the final stage of the Fitter. The following table describes what you can preserve or reuse from each Compiler snapshot:

Table 2.  Description of Preservation and Reuse with each Compiler Snapshot
Snapshot Description Preserve/Reuse
Synthesized Preserves a synthesized netlist that represents the logic for a design partition.
  • Applies to .qdb and partition preservation.
  • Preserves logical boundaries.
  • No physical preservation.
  • Supports snapshot reuse across devices in the same family.
Final Preserves final device utilization, placement, routing, and hold time fix-up.
  • Applies to .qdb files and partition preservation.
  • Intel® Arria® 10 High-Speed/Low-Power Tile settings do not change.
  • Intel® Stratix® 10 retimed register locations do not change.
  • Does not preserve global signals or signals that cross partition boundaries.
  • Supports snapshot reuse across projects targeting the same device.

When reusing snapshots in a project targeting another device in the same family, you can only reuse the Synthesized snapshot, rather than the Final snapshot. The following additional limitations apply to reuse of snapshot across devices within the same family.

Table 3.  Limitations on Snapshot Reuse Across Devices in Family
Snapshot Reuse Scenario Result
Import of Final snapshot across devices in same family. The Fitter issues an error during compilation in the Consumer project.
Import of Synthesized snapshot across devices in different families
Import from or export to a project that targets the AUTO device The Compiler supports this scenario and issues no error if target device is within the same family.
Import of the root_partition (device periphery) Synthesized snapshot The Compiler supports this scenario as long as the imported partition contains no invalid Fitter assignments (such as conflicting Logic Lock regions). Invalid Fitter assignments produce unexpected results.
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