Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 9/26/2022

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3.6.9. Using Fitter Overconstraints

Fitter overconstraints are timing constraints that you adjust to overcome modeling inaccuracies, mis-correlation, or other deficiencies in logic optimization. You can overconstrain setup and hold paths in the Fitter to force more aggressive timing optimization of specific paths.

Overconstraints for Intel® Stratix® 10 Designs

When designing for Intel® Stratix® 10 devices, you can target specific nodes with Fitter overconstraints to prevent the Compiler from retiming and optimizing these paths (nodes may have multiple timing requirements and the Compiler treats as “don’t touch”). If the constraint targets specific nodes, use the is_post_route Tcl function. This function allows you to apply overconstraints and adjust slack for modules of the Fitter (Plan, Place, Route), while allowing post-route retiming and not affecting sign-off timing analysis.

# Example Fitter overconstraint targeting specific nodes (allows for post-route retiming)
if { ! [is_post_route]} {
  set_max_delay -from ${my_src_regs} -to ${my_dst_regs} 1ns
Note: The is_post_route function is inclusive. To exclude the function, use the negation syntax (!).

Overconstraints for Designs that Target All Other Device Families

You can assign Fitter overconstraints that check the name of the current executable, (either quartus_fit or quartus_sta) to apply different constraints for Fitter optimization and sign-off timing analysis.

set fit_flow 0
if { $::TimingAnalyzerInfo(nameofexecutable) == "quartus_fit" } {
   set fit_flow 1
if {$fit_flow} {
  # Example Fitter overconstraint targeting specific nodes (restricts retiming)
  set_max_delay -from ${my_src_regs} -to ${my_dst_regs} 1ns

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