ID 683243
Date 9/26/2022
Public

## 3.6.6.1. Input Constraints (set_input_delay)

Input constraints specify delays for all external signals feeding the FPGA. Specify input requirements for all input ports in your design.
set_input_delay -clock { clock } -clock_fall -fall -max 20 foo

Use the Set Input Delay (set_input_delay) constraint to specify external input delay requirements. Specify the Clock name (-clock) to reference the virtual or actual clock. You can specify a clock to allow the Timing Analyzer to correctly derive clock uncertainties for interclock and intraclock transfers. The clock defines the launching clock for the input port. The Timing Analyzer automatically determines the latching clock inside the device that captures the input data, because all clocks in the device are defined.

Figure 104. Input Delay Diagram
Figure 105. Input Delay Calculation

If your design includes partition boundary ports, you can use the -blackbox option with set_input_delay to assign input delays. The -blackbox option creates a new keeper timing node with the same name as the boundary port. This new node permits the propagation of timing paths through the original boundary port and acts as a set_input_delay constraint. The new keeper timing nodes display when you use the get_keepers command. You can remove these black box constraints with remove_input_delay -blackbox.