Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 9/26/2022

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3.6.10. Example Circuit and SDC File

The following .sdc file demonstrates constraining a dual-clock, phase-locked loop (PLL) example that illustrates. and other common synchronous design elements.

Basic .sdc Constraints Example

# Create clock constraints
create_clock -name clockone -period 10.000Ns [get_ports {clk1}]
create_clock -name clocktwo -period 10.000Ns [get_ports {clk2}]
# Create virtual clocks for input and output delay constraints
create clock -name clockone_ext -period 10.000Ns
create clock -name clocktwo_ext -period 10.000Ns
# derive PLL clocks to create the altpll0| clock referenced later
# derive clock uncertainty
# Specify that clockone and clocktwo are unrelated by assigning
# them to separate asynchronous groups
set_clock_groups \    
  -asynchronous \
  -group {clockone} \    
  -group {clocktwo altpll0|altpll_component|auto_generated|pll1|clk[0]}         
# set input and output delays
set_input_delay -clock { clockone_ext } -max 4 [get_ports {data1}]
set_input_delay -clock { clockone_ext } -min -1 [get_ports {data1}]
set_input_delay -clock { clockone_ext } -max 4 [get_ports {data2}]
set_input_delay -clock { clockone_ext } -min -1 [get_ports {data2}]
set_output_delay -clock { clocktwo_ext } -max 6 [get_ports {dataout}]
set_output_delay -clock { clocktwo_ext } -min -3 [get_ports {dataout}]

The .sdc file contains the following basic constraints that you typically include for most designs:

  • Definitions of clockone and clocktwo as base clocks, and assignment of those constraints to nodes in the design.
  • Definitions of clockone_ext and clocktwo_ext as virtual clocks, which represent clocks driving external devices interfacing with the FPGA.
  • Automated derivation of generated clocks on PLL outputs.
  • Derivation of clock uncertainty.
  • Specification of two clock groups, the first containing clockone and its related clocks, the second containing clocktwo and the output of the PLL. This specification overrides the default analysis of all clocks in the design as related to each other.
  • Specification of input and output delays for the design.
Figure 160. Dual-Clock Design Constraint Example