126.96.36.199.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
The following timing diagram shows the default setup check analysis the Timing Analyzer performs:
The setup relationship in this example demonstrates that the data is not launched at edge one, and the data that is launched at edge three must be captured; therefore, you can relax the setup requirement. To correct the default analysis, you shift the launch edge by two clock periods with a start multicycle setup exception of three.
The following multicycle exception adjusts the default analysis in this example:
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \
-setup -start 3
The following timing diagram shows the preferred setup relationship for this example:
The Timing Analyzer performs the following calculation to determine the hold check:
The following timing diagram shows the default hold check analysis the Timing Analyzer performs for a start multicycle setup value of three:
In this example, the hold check two is too restrictive. The data is launched next by the edge at 10 ns and must check against the data captured by the current latch edge at 12 ns, which does not occur in hold check two. To correct the default analysis, you must specify a multicycle hold exception of one.