Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 9/26/2022

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Document Table of Contents Report Fmax Summary

The Timing Analyzer Reports > Datasheet > Report Fmax Summary command generates a report panel showing the potential maximum frequency for every clock in your design. The Fmax column reports the fastest frequency that your clock can run, and still pass report_timing -setup -intra_clock with a slack of 0. The equivalent console command is report_clock_fmax_summary.
Fmax Summary Report

Note: The related get_clock_fmax_info command returns a Tcl list, which is useful for scripting and parsing. Refer to get_clock_fmax_info (::quartus::sta) in Intel Quartus Prime Pro Edition User Guide Scripting.

fMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, fMAX is computed as if the rising and falling edges of the clock are scaled along with fMAX, such that duty cycle (by percentage) is maintained.

However, the Fmax report does not indicate whether your design meets timing for recovery, removal, nor setup or hold without the intra_clock option. For these reasons, always make sure to view the Setup, Hold, Recovery, Removal, and Min Pulse Width slack summaries to determine whether your design meets timing.

The Restricted Fmax column reports the lesser of the following values:

  • The fastest frequency that your clock can run, and still pass report_timing -hold -intra_clock with a slack of 0 or report_min_pulse_width with a slack of 0.
  • The Fmax column value.2

Restricted Fmax considers hold timing in addition to setup timing, as well as minimum pulse and minimum period restrictions. Similar to unrestricted fMAX, the analysis computes the restricted fMAX as if the rising and falling edges of the clock scale along with fMAX, such that the duty cycle (in terms of a percentage) is maintained.

The Restricted Fmax may display text indicating any of the following limiting factors:

  • Limit due to hold check
  • Limit due to minimum pulse width restriction
  • Limit due to high minimum pulse width restriction
  • Limit due to low minimum pulse width restriction

Typically, hold checks do not limit the maximum frequency (fMAX) because the checks are for same-edge relationships, and therefore independent of clock frequency. For example, when launch equals zero and latch equals zero. However, with an inverted clock transfer, or a multicycle transfer, the hold relationship is not a same-edge transfer and changes with the clock frequency.

Refer to the timing reports, such as those that you can generate using report_timing, or using minimum pulse width reports via the report_min_pulse_width command for details of specific paths, registers, or ports.

2 The Restricted Fmax column never reports a value higher than the Fmax column.