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2.2.5. Multicycle Path Analysis
A multicycle path occurs between the input registers of a multiplier, and an output register with a destination that latches data on every other clock edge.
A register-to-register path is for the default setup and hold relationship. Also, for the respective timing diagrams for the source and destination clocks and the default setup and hold relationships, when the source clock, src_clk, has a period of 10 ns and the destination clock, dst_clk, has a period of 5 ns. The default setup relationship is 5 ns; the default hold relationship is 0 ns.
To accommodate the system requirements, you can modify the default setup and hold relationships by specifying a multicycle timing constraint to a register-to-register path.
The exception has a multicycle setup assignment of two to use the second occurring latch edge; in this example, to 10 ns from the default value of 5 ns.
Multicycle Clock Hold
Multicycle Clock Setup
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