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2.2.1. Timing Path and Clock Analysis 2.2.2. Clock Setup Analysis 2.2.3. Clock Hold Analysis 2.2.4. Recovery and Removal Analysis 2.2.5. Multicycle Path Analysis 2.2.6. Metastability Analysis 2.2.7. Timing Pessimism 2.2.8. Clock-As-Data Analysis 2.2.9. Multicorner Timing Analysis 2.2.10. Time Borrowing
3.1. Timing Analysis Flow 3.2. Step 1: Specify Timing Analyzer Settings 3.3. Step 2: Specify Timing Constraints 3.4. Step 3: Run the Timing Analyzer 3.5. Step 4: Analyze Timing Reports 3.6. Applying Timing Constraints 3.7. Timing Analyzer Tcl Commands 3.8. Timing Analysis of Imported Compilation Results 3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
126.96.36.199. Report Fmax Summary 188.8.131.52. Report Timing 184.108.40.206. Report Timing By Source Files 220.127.116.11. Report Data Delay 18.104.22.168. Report Net Delay 22.214.171.124. Report Clocks and Clock Network 126.96.36.199. Report Clock Transfers 188.8.131.52. Report Metastability 184.108.40.206. Report CDC Viewer 220.127.116.11. Report Asynchronous CDC 18.104.22.168. Report Logic Depth 22.214.171.124. Report Neighbor Paths 126.96.36.199. Report Register Spread 188.8.131.52. Report Route Net of Interest 184.108.40.206. Report Retiming Restrictions 220.127.116.11. Report Register Statistics 18.104.22.168. Report Pipelining Information 22.214.171.124. Report Time Borrowing Data 126.96.36.199. Report Exceptions and Exceptions Reachability 188.8.131.52. Report Bottlenecks
3.6.1. Recommended Initial SDC Constraints 3.6.2. SDC File Precedence 3.6.3. Modifying Iterative Constraints 3.6.4. Using Entity-bound SDC Files 3.6.5. Creating Clocks and Clock Constraints 3.6.6. Creating I/O Constraints 3.6.7. Creating Delay and Skew Constraints 3.6.8. Creating Timing Exceptions 3.6.9. Using Fitter Overconstraints 3.6.10. Example Circuit and SDC File
184.108.40.206.1. Default Multicycle Analysis 220.127.116.11.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 18.104.22.168.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 22.214.171.124.4. Same Frequency Clocks with Destination Clock Offset 126.96.36.199.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 188.8.131.52.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 184.108.40.206.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 220.127.116.11.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
3.6.3. Modifying Iterative Constraints
Iteratively modify .sdc constraints and reanalyze the timing results to ensure that you have complete constraints for your design.
- Click Tools > Timing Analyzer.
- Generate the reports you want to analyze. Double-click Report All Summaries under Macros to generate setup, hold, recovery, and removal summaries, summaries for supported reports, and a list of all the defined clocks in the design. These summaries cover all paths you constrain in your design. Whenever modifying or correcting constraints, generate the Constraint Diagnostic reports to identify unconstrained parts of your design, or ignored constraints.
- Analyze the results in the reports. When you are modifying constraints, rerun the reports to find any unexpected results. For example, a cross-domain path might indicate that you forgot to cut a transfer by including a clock in a clock group.
- Create or edit the appropriate constraints in your .sdc file and save the file.
- Double-click Reset Design in the Tasks pane. This removes all constraints from your design. Removing all constraints from your design allows rereading the .sdc files, including your changes.
- Regenerate the reports you want to analyze.
- Reanalyze the results.
- Repeat steps 4-7 as necessary.
This method performs timing analysis using new constraints, without any change to logic placement. While the Fitter uses the original constraints for place and route, the Timing Analyzer applies the new constraints. If you see any failing timing against the new constraints, run place-and-route again.
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