Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

ID 683232
Date 5/27/2022

Reference Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 5.  Reference Pins
Pin Name Pin Functions Pin Description Connection Guidelines
GND Ground Device ground pins.

Intel recommends you to tie REFGND to the GND pin with an isolating ferrite bead for the best ADC performance.

Connect all GND pins to the board GND plane.

NC No Connect Do not drive signals into these pins. When designing for device migration you may connect these pins to power, ground, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern, leave these pins floating.
DNU Do Not Use Do Not Use (DNU). Do not connect to power, GND, or any other signal. These pins must be left floating.