Example 6— Intel® MAX® 10 (Single Supply) FPGA
Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Power Pin Name | Regulator Count | Voltage Level (V) | Supply Tolerance | Power Source | Regulator Sharing | Notes |
---|---|---|---|---|---|---|
VCC_ONE | 1 | 3.0/3.3 | ± 5% | Switcher (*) | Share | Both VCCA and VCC_ONE must share a single power source using proper isolation filter. |
VCCA | Isolate | |||||
VCCIO1B | 2 | 3.0/3.3 | ± 5% | Switcher (*) | Share | You have the option to share VCCIO1A with VCCIO1B using proper isolation filter. |
VCCIO1A | Isolate | |||||
VCCIO[2..8] | 3 | Varies | ± 5% | Switcher (*) | Share | Individual power rail. |
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines.
Notes:
- Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
- Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® MAX® 10 FPGA device is provided in Figure 6.
- Refer to the Intel® MAX® 10 FPGA Configuration User Guide for maximum ramp rate requirement.
Figure 6. Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 1.0V/1.2V/1.35V/1.5V/1.8V/2.5V (E144, M153, U169, and U324 Packages)