MAX® 10 FPGA Device Family Pin Connection Guidelines

Download PDF
ID 683232
Date 8/20/2024
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Device Family Pin Connection Guidelines x
MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for MAX® 10 FPGA Devices Document Revision History for the MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins MAX® 10 (Single Supply) FPGA MAX® 10 (Dual Supply) FPGA Notes to the MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for MAX® 10 FPGA Devices x
Example 1— MAX® 10 (Dual Supply) FPGA Example 2— MAX® 10 (Dual Supply) FPGA Example 3— MAX® 10 (Dual Supply) FPGA Example 4— MAX® 10 (Single Supply) FPGA Example 5— MAX® 10 (Single Supply) FPGA Example 6— MAX® 10 (Single Supply) FPGA
MAX® 10 FPGA Device Family Pin Connection Guidelines

Notes to the MAX® 10 FPGA Pin Connection Guidelines

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.

Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. These pin connection guidelines are created based on the MAX® 10 FPGA device family.
  2. The number of dedicated global clocks for each device density is different.
  3. The unused pins must be connected as specified in the Quartus® Prime software settings. The default Quartus® Prime setting for unused pins is 'As inputs tri-stated with weak pull-up resistors', unless for specific pins that the Quartus® Prime software connects them to GND automatically.
  4. Capacitance values for the power supply decoupling capacitors should be selected after consideration of the amount of power needed to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to "Equivalent Series Inductance" of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To assist in decoupling analysis, Altera's "Power Distribution Network (PDN) Design Tool" serves as an excellent decoupling analysis tool. The PDN design tool can be obtained at Power Distribution Network Design Tool.
    Table 9.  Transient Current and Voltage Ripple for MAX® 10 DevicesTo calculate the target impedance of each MAX® 10 device supply, you should use the following transient current and voltage ripple percentages. Setting Ftarget to 70 MHz or higher should result in a robust PDN.
    MAX® 10 Supply Rail Transient Current (%) Voltage Ripple (%)
    VCC 50 5
    VCCIO 100 5
    VCCA 10 5
    VCCD_PLL 10 3
    VCCA_ADC 50 2
    VCCINT 50 3
  5. Use separate power islands for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent methods. If using a ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state current for the supply it is connected to (VCCA or VCCD_PLL) and high impedance at 100 MHz.
  6. The VCCA power island can be decoupled with a combination of decoupling capacitors. Please refer to the Power Distribution Network Design Tool to determine the decoupling capacitors value. Use 0402 package for 0.1 uF and smaller capacitors for lower mounting inductance. Place 0.1 uF and smaller capacitors as close to the device as possible. On-board capacitors do not decouple higher than 100 MHz due to "Equivalent Series Inductance" of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To minimize impact on jitter, a 20 mV ripple voltage was used in the analysis for VCCA decoupling.
  7. The VCCD_PLL power island can be decoupled with a combination of decoupling capacitors. Refer to the "Power Distribution Network Design Tool" at Power Distribution Network Design Tool to determine the decoupling capacitors value. Place 0.1 uF and smaller capacitors as close to the device as possible. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To minimize impact on jitter, a 20 mV ripple voltage was used in the analysis for VCCD_PLL decoupling.
  8. All configuration pins used in user mode are low-speed I/Os.
  9. Low Noise Switching Regulator—defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Altera requirement. However, Altera does require the Line Regulation and Load Regulation meet the following specifications:
    • Line Regulation < 0.4%
    • Load Regulation < 1.2%
  10. If you enable the Configure device from CFM0 only option in the Quartus® Prime software when generating the POF file, the FPGA always loads the configuration image 0 without sampling the physical CONFIG_SEL pin during power up.
Level Two Title