MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 8/20/2024
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Device Family Pin Connection Guidelines x
MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for MAX® 10 FPGA Devices Document Revision History for the MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins MAX® 10 (Single Supply) FPGA MAX® 10 (Dual Supply) FPGA Notes to the MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for MAX® 10 FPGA Devices x
Example 1— MAX® 10 (Dual Supply) FPGA Example 2— MAX® 10 (Dual Supply) FPGA Example 3— MAX® 10 (Dual Supply) FPGA Example 4— MAX® 10 (Single Supply) FPGA Example 5— MAX® 10 (Single Supply) FPGA Example 6— MAX® 10 (Single Supply) FPGA
MAX® 10 FPGA Device Family Pin Connection Guidelines

MAX® 10 FPGA Pin Connection Guidelines

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