Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

ID 683232
Date 5/27/2022
Public

Example 2— Intel® MAX® 10 (Dual Supply) FPGA

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 11.  Power Supply Sharing Guidelines for Intel® MAX® 10 (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5VExample Requiring 3 Power Regulators
Power Pin Name Regulator Count Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1 1.2 ± 50mV Switcher (*) Share You have the option to share VCCINT and VCCD_PLL with VCC with proper isolation filters.
VCCINT Isolate
VCCD_PLL Isolate
VCCA 2 2.5 ± 5% Switcher (*) Share You have the option to share VCCA_ADC with VCCA with proper isolation filters.
VCCA_ADC Isolate
VCCIO1B 3 2.5 ± 5% Switcher (*) Share You have the option to share VCCIO1B and VCCIO[2..8] when these pins are powered up at 2.5V.
VCCIO[2..8]
VCCIO1A Isolate You have the option to share VCCIO1A with VCCIO1B and VCCIO[2..8] using proper isolation filter.

(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines.

Notes:

  1. Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
  2. Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® MAX® 10 FPGA device is provided in Figure 2.
  3. For LPDDR2 interface targeting 200MHz,you need to constraint the memory device I/O and core power supply to ± 3% variation.
  4. Refer to the Intel® MAX® 10 FPGA Configuration User Guide for maximum ramp rate requirement.
Figure 2. Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Dual Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up at 2.5V