Example 2— Intel® MAX® 10 (Dual Supply) FPGA
|Power Pin Name||Regulator Count||Voltage Level (V)||Supply Tolerance||Power Source||Regulator Sharing||Notes|
|VCC||1||1.2||± 50mV||Switcher (*)||Share||You have the option to share VCCINT and VCCD_PLL with VCC with proper isolation filters.|
|VCCA||2||2.5||± 5%||Switcher (*)||Share||You have the option to share VCCA_ADC with VCCA with proper isolation filters.|
|VCCIO1B||3||2.5||± 5%||Switcher (*)||Share||You have the option to share VCCIO1B and VCCIO[2..8] when these pins are powered up at 2.5V.|
|VCCIO1A||Isolate||You have the option to share VCCIO1A with VCCIO1B and VCCIO[2..8] using proper isolation filter.|
(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines.
- Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
- Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® MAX® 10 FPGA device is provided in Figure 2.
- For LPDDR2 interface targeting 200MHz,you need to constraint the memory device I/O and core power supply to ± 3% variation.
- Refer to the Intel® MAX® 10 FPGA Configuration User Guide for maximum ramp rate requirement.
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