Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 5/27/2022
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Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines x
Intel® MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins Intel® MAX® 10 (Single Supply) FPGA Intel® MAX® 10 (Dual Supply) FPGA Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices x
Example 1— Intel® MAX® 10 (Dual Supply) FPGA Example 2— Intel® MAX® 10 (Dual Supply) FPGA Example 3— Intel® MAX® 10 (Dual Supply) FPGA Example 4— Intel® MAX® 10 (Single Supply) FPGA Example 5— Intel® MAX® 10 (Single Supply) FPGA Example 6— Intel® MAX® 10 (Single Supply) FPGA
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Clock and PLL Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 1.  Clock and PLL Pins
Pin Name Pin Functions Pin Description Connection Guidelines
CLK [0..7]p Clock, I/O

Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins. When these clock input pins are used as single-ended pins, you can disregard the p notation.

CLK[0..7]p pins can function as regular I/O pins.

Connect unused pins to the VCCIO of the bank in which the pins reside or GND.

See Notes 2 and 3.
CLK[0..7]n Clock, I/O

Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. When these clock input pins are used as single-ended pins, you can disregard the n notation.

CLK[0..7]n pins can function as regular I/O pins.

Connect unused pins to the VCCIO of the bank in which the pins reside or GND.

See Notes 2 and 3.
DPCLK[0..3] I/O, Input DPCLK pins can connect to the global clock network for high fan-out control signals such as clocks, asynchronous clears, presets, and clock enables. DPCLK pins cannot feed a PLL input.

Connect unused pins to the VCCIO of the bank they reside in or GND.

These pins can function as regular I/O pins.

See Note 3.
PLL_[L,R,B,T]_CLKOUTp I/O, Output

Optional positive terminal for external clock outputs from PLL [1..4]. These pins can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output.

  • PLL_L_CLKOUTp is referring to PLL_1.
  • PLL_R_CLKOUTp is referring to PLL_2.
  • PLL_T_CLKOUTp is referring to PLL_3.
  • PLL_B_CLKOUTp is referring to PLL_4.

The availability for PLL_[L,R,B,T]_CLKOUTp pins varies for each device density and package combination. For details, refer to the specific device pinout file.

Connect unused pins to GND.

These pins can function as regular I/O pins.

See Note 3.
PLL_[L,R,B,T]_CLKOUTn I/O, Output

Optional negative terminal for external clock outputs from PLL [1..4]. These pins can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output.

  • PLL_L_CLKOUTn is referring to PLL_1.
  • PLL_R_CLKOUTn is referring to PLL_2.
  • PLL_T_CLKOUTn is referring to PLL_3.
  • PLL_B_CLKOUTn is referring to PLL_4.

The availability for PLL_[L,R,B,T]_CLKOUTn pins varies for each device density and package combination. For details, refer to the specific device pinout file.

Connect unused pins to GND.

These pins can function as regular I/O pins.

See Note 3.
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