MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 8/20/2024
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Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Device Family Pin Connection Guidelines x
MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for MAX® 10 FPGA Devices Document Revision History for the MAX® 10 FPGA Device Family Pin Connection Guidelines
MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins MAX® 10 (Single Supply) FPGA MAX® 10 (Dual Supply) FPGA Notes to the MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for MAX® 10 FPGA Devices x
Example 1— MAX® 10 (Dual Supply) FPGA Example 2— MAX® 10 (Dual Supply) FPGA Example 3— MAX® 10 (Dual Supply) FPGA Example 4— MAX® 10 (Single Supply) FPGA Example 5— MAX® 10 (Single Supply) FPGA Example 6— MAX® 10 (Single Supply) FPGA
MAX® 10 FPGA Device Family Pin Connection Guidelines

Analog Input Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 6.  Analog Input Pins
Pin Name Pin Functions Pin Description Connection Guidelines
ADC[1..2]IN[1..16] I/O, Input

These multi-purpose pins support single-ended analog input or, bank does not support both analog and digital signals simultaneously. When not used as analog input pins, these pins can be used as any other digital I/O pins.

The ADCIN[8] and ADCIN[16] pins support the prescalar feature.

For 10M08 and 10M16 devices, the ADC1IN[1..8] pins are available for the single power supply devices and the ADC1IN[1..16] pins are available for 10M08U324 devices. The ADC1IN[1..16] pins are available for the dual power supply devices.

For 10M25 and 10M50 devices, the ADC1IN[1..8] and ADC2IN[1..8] pins are available for both single and dual power supply devices.

All digital I/O pins are tristated if any of these pins is configured as an analog input pin. For unused ADCIN pins, Altera recommends you to connect them to GND.

No parallel routing between analog input signals and I/O traces. The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. Route the analog input signal adjacent to the REFGND.

Total RC value including package, trace, and driver parasitic values should be less than 42.4 ns. This is to ensure the input signal is fully settled during the sampling phase.

Low pass filter is required for each analog input pin. The filter ground reference is REFGND.

For details about the board design guidelines, refer to the MAX® 10 Analog to Digital Converter User Guide .

ADC_VREF Input Analog-to-digital converter (ADC) voltage reference input.

Tie the ADC_VREF pin to an external accurate voltage reference source. If you are not using the external reference, this pin is a no connect (NC).

No parallel routing between analog input signals and I/O traces. The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz.

For more information, refer to the Guidelines: Board Design for ADC Reference Voltage Pin section of the MAX® 10 Analog to Digital Converter User Guide .

ANAIN[1] Input This is a dedicated single-ended analog input pin for ADC1.

If this pin is not used, Altera recommends you to connect it to GND.

No parallel routing between analog input signals and I/O traces. The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. Route the analog input signal adjacent to the REFGND.

Total RC value including package, trace, and driver parasitic values should be less than 42.4 ns. This is to ensure the input signal is fully settled during the sampling phase.

Low pass filter is required for each analog input pin. The filter ground reference is REFGND.

For details about the board design guidelines, refer to the MAX® 10 Analog to Digital Converter User Guide .

ANAIN[2] Input

This is a dedicated single-ended analog input pin for ADC2.

This pin is not available in each device density and package combination. For details, refer to the specific device pinout file.

If this pin is not used, Altera recommends you to connect it to GND. No parallel routing between analog input signals and I/O traces. The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. The RC filter ground reference is REFGND.

Total RC value including package, trace, and driver parasitic values should be less than 42.4 ns. This is to ensure the input signal is fully settled during the sampling phase.

Low pass filter is required for each analog input pin. The filter ground reference is REFGND.

For more information, refer to the MAX® 10 Analog to Digital Converter User Guide .

REFGND Input This pin is the ADC ground reference pin for analog pins.

Altera recommends you to tie REFGND to the GND pin with an isolating ferrite bead for the best ADC performance.

If you are not using ADC, tie this pin directly to GND.

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