Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

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ID 683221
Date 11/10/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP 2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives 11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP x
1.1. Low Latency 40G for ASIC Proto Ethernet IP Core Supported Features 1.2. Device Family Support 1.3. Low Latency 40G for ASIC Proto Ethernet IP Core Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Adding the External TX MAC PLL 3.5.4. Placement Settings for the Low Latency 40G for ASIC Proto Ethernet Core
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G for ASIC Proto Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency 40G for ASIC Proto Ethernet Core Functional Description x
4.1.1. Low Latency 40G for ASIC Proto Ethernet Core TX MAC Datapath 4.1.2. Low Latency 40G for ASIC Proto Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency 40G for ASIC Proto Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. Low Latency 40G for ASIC Proto Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. Transceivers Signals 6.6. Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Statistics Registers
7.4. Statistics Registers x
7.4.1. TX Statistics Registers 7.4.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History

2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters

The Low Latency 40G for ASIC Proto Ethernet parameter editor has an IP tab and the Main tab.

The Low Latency 40G for ASIC Proto Ethernet parameter editor also includes an Example Design tab. For information about that tab, refer to the Low Latency 40G for ASIC Proto Ethernet IP Design Example User Guide .

Figure 2. Example IP Tab in the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Parameter Editor
Table 8.   Low Latency 40G for ASIC Proto Ethernet IP Core Parameters: Main Tab
Parameter Range Default Setting Description
General
Target transceiver tile

H-Tile

The tile type of the Intel® Quartus® Prime project specific target device. Specifies the transceiver tile on your target device. The Device setting of the Intel® Quartus® Prime project in which you generate the IP core determines the transceiver tile type.
Protocol speed 40GbE 40GbE Selects the Ethernet data rate.
Ready latency 0, 3 0 Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the l2_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the TX datapath.

PCS/PMA Options
Use external TX MAC PLL Enabled, Disabled Disabled When enabled, the IP core is configured to expect an input clock to drive the TX MAC. The input clock signal is clk_txmac_in.
Enable SyncE Enabled, Disabled Disabled Exposes the RX recovered clock as an output signal. This feature supports the Synchronous Ethernet standard described in the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) G.8261, G.8262, and G.8264 recommendations.
PHY reference frequency

322.265625 MHz, 644.53125 MHz

644.53125 MHz

Sets the expected incoming PHY clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100ppm).
VCCR_GXB and VCCT_GXB supply voltage for the transceiver 1_0V, 1_1V 1_0V

Specifies whether the transceiver supply voltage is 1.0 V or 1.1 V. The supply voltage must match the voltage you specify for this parameter.

MAC Options
Select USER MAC mode MAC+PCS, PCS_Only MAC+PCS Specifies the selection of MAC with the IP.
  • MAC+PCS: The generated IP includes the MAC.
  • PCS_Only: The generated IP doesn't contain the MAC.
Enable TX CRC insertion Enabled, Disabled Enabled When enabled, TX MAC computes and inserts the CRC-32 checksum in the out-going Ethernet frame. When disabled, the TX MAC does not compute a 32-bit FCS in the TX MAC frame. Instead, the client must provide frames with at least 64 bytes, plus the Frame Check Sequence (FCS).
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP core implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Ethernet Standard. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable MAC stats counters Enabled, Disabled Enabled When enabled, the IP core includes statistics counters that characterize TX and RX traffic. The statistics module also supports shadow requests that verify counts by taking snapshots of intermediate results.
Enable Strict SFD check Enabled, Disabled Disabled When enabled, the IP core can implement strict SFD checking, depending on register settings.
Flow Control Options
Enable MAC flow control Enabled, Disabled Disabled When enabled, the IP core implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames.
Number of queues in priority flow control 1-8 8 Specifies the number of queues used in managing flow control.
Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint (NPDME) Enabled, Disabled Disabled
If enabled, the IP core turns on the following features in the Native PHY IP core that is included in the Low Latency 40G for ASIC Proto Ethernet IP core:
  • Enable Native PHY Debug Master Endpoint (NPDME)
  • Enable capability registers

If turned off, the IP core is configured without these features.

For information about these Intel® Stratix® 10 features, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.

Enable JTAG to Avalon Master Bridge Enabled, Disabled Disabled

If turned on, the IP core includes a JTAG to Avalon® memory-mapped interface master bridge connecting internally to status and reconfiguration registers.

This allows you to run the Ethernet Link Inspector using the System Console.

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