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1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. TX PCS Interface to User Logic
6.4. RX PCS Interface to User Logic
6.5. Transceivers Signals
6.6. Transceiver Reconfiguration Signals
6.7. Avalon® Memory-Mapped Management Interface
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
6.10. Clocks
6.11. Flow Control Interface
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4.1.2.3. Length/Type Field Processing
This two-byte header represents either the length of the payload or the type of MAC frame.
- Length/type >= 0x600—The field represents the frame type. The following frame types are possible:
- Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC RX continues to check the frame and payload lengths.
- Length/type = 0x8808—Control frames. The next two bytes are the Opcode field that indicates the type of control frame. For pause frames (Opcode = 0x0001) and PFC frames (Opcode = 0x0101), the MAC RX proceeds with pause frame processing.
- For other field values, the MAC RX forwards the receive frame to the client.
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