Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

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ID 683221
Date 11/10/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP 2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives 11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP x
1.1. Low Latency 40G for ASIC Proto Ethernet IP Core Supported Features 1.2. Device Family Support 1.3. Low Latency 40G for ASIC Proto Ethernet IP Core Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Adding the External TX MAC PLL 3.5.4. Placement Settings for the Low Latency 40G for ASIC Proto Ethernet Core
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G for ASIC Proto Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency 40G for ASIC Proto Ethernet Core Functional Description x
4.1.1. Low Latency 40G for ASIC Proto Ethernet Core TX MAC Datapath 4.1.2. Low Latency 40G for ASIC Proto Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency 40G for ASIC Proto Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. Low Latency 40G for ASIC Proto Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. Transceivers Signals 6.6. Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Statistics Registers
7.4. Statistics Registers x
7.4.1. TX Statistics Registers 7.4.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History

6.9. Reset Signals

The IP core has three external hard reset inputs. These resets are asynchronous and are internally synchronized. Assert resets for ten clk_txmac clock cycles or until you observe the effect of their specific reset. Asserting the external hard reset csr_rst_n returns control and status registers to their original values, with the exception of the statistics counters. rx_pcs_ready and tx_lanes_stable are asserted when the IP core has exited reset successfully.
Table 21.   Reset Signals

Signal

Direction

Description

tx_rst_n Input Active low hard reset signal. Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the deassertion of the tx_lanes_stable output signal.
rx_rst_n Input

Active low hard reset signal. Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the deassertion of the rx_pcs_ready output signal.

csr_rst_n Input

Active low hard global reset. Resets the full IP core. Resets the TX MAC, RX MAC, TX PCS, RX PCS, transceivers, and control and status registers, except the statistics counters. This reset leads to the deassertion of the tx_lanes_stable and rx_pcs_ready output signals.

tx_mac_sclr Output

Soft reset in PCS variations. Resets the TX interface, including the TX PCS.

rx_mac_sclr Output Soft reset in PCS variations. Resets the RX interface, including the RX PCS.
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