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Ixiasoft
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Ixiasoft
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
Updated for: |
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Intel® Quartus® Prime Design Suite 20.3 |
IP Version 19.1.0 |
The Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP core implements the IEEE 802.3-2010 40G Ethernet Standard. The IP core includes options to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
IP Core Variation | Client Interface Type | Client Interface Width (Bits) |
---|---|---|
MAC+PCS | Avalon® streaming interface (Avalon ST) | 128 |
PCS_Only | Media Independent Interface (MII) | 128 |
The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) functions. The PHY comprises the PCS and PMA.
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