Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

ID 683221
Date 11/10/2022
Document Table of Contents

3.5.3. Adding the External TX MAC PLL

If you turn on Use external TX MAC PLL in the Low Latency 40G for ASIC Proto Ethernet parameter editor, you must connect the clk_txmac_in input port to a clock source, usually a PLL on the device.

The clk_txmac_in signal drives the clk_txmac clock in the IP core TX MAC and PHY. If you turn off this parameter, the clk_txmac_in input clock signal is not available.

The required TX MAC clock frequency is 312.5 MHz. User logic must drive clk_txmac_in from a PLL whose input is the PHY reference clock, clk_ref.