Visible to Intel only — GUID: vky1471560999502
Ixiasoft
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. TX PCS Interface to User Logic
6.4. RX PCS Interface to User Logic
6.5. Transceivers Signals
6.6. Transceiver Reconfiguration Signals
6.7. Avalon® Memory-Mapped Management Interface
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
6.10. Clocks
6.11. Flow Control Interface
Visible to Intel only — GUID: vky1471560999502
Ixiasoft
7.4. Statistics Registers
The Low Latency 40G for ASIC Proto Ethernet statistics registers count Ethernet traffic and errors. The 64-bit statistics registers are designed to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is functioning properly. The statistics registers check the size of frames, which includes the following fields:
- Size of the destination address
- Size of the source address
- Size of the data
- Four bytes of CRC
The statistics counters module is a synthesis option. The statistics registers are counters that are implemented inside the CSR. When you turn on the Enable MAC stats counters parameter in the Low Latency 40G for ASIC Proto Ethernet parameter editor, the counters are implemented in the CSR. When you turn off the Enable MAC stats counters parameter in the Low Latency 40G for ASIC Proto Ethernet parameter editor, the counters are not implemented in the CSR, and read access to the counters returns undefined results.
After system power-up, the statistics counters have random values. You must clear these registers and confirm the system is stable before using their values. You can clear the registers with the csr_rst_n input signal, or with the configuration registers at offsets 0x845 and 0x945.
The configuration register at offset 0x845 allows you to clear all of the TX statistics counters. The configuration register at offset 0x945 allows you to clear all of the RX statistics counters. If you exclude these registers, you can monitor the statistics counter increment vectors that the IP core provides at the client side interface and maintain your own counters.
Reading the value of a statistics register does not affect its value.
To ensure that the counters you read are consistent, you should issue a shadow request to create a snapshot of all of the TX or RX statistics registers, by setting bit [2] of the configuration register at offset 0x845 or 0x945, respectively. Until you reset this bit, the counters continue to increment but the readable values remain constant. You can read bit [1] of the status register at offset 0x846 or 0x946, respectively, to confirm your shadow request has been granted or released.