Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

ID 683221
Date 11/10/2022
Document Table of Contents

1.1. Low Latency 40G for ASIC Proto Ethernet IP Core Supported Features

The Low Latency 40G for ASIC Proto Ethernet IP core supports the following features:

  • Parameterizable through the IP Catalog available with the Intel® Quartus® Prime Pro Edition software.
  • Designed to the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
  • Soft PCS logic that interfaces seamlessly to Intel® FPGA 10.3125 gigabits per second (Gbps) serial transceivers.
  • Standard XLAUI external interface consisting of FPGA hard serial transceiver lanes operating at 10.3125 Gbps.
  • Supports Synchronous Ethernet (SyncE) by providing an optional CDR recovered clock output signal to the device fabric.
  • Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
  • Avalon-ST data path interface connects to client logic with the start of frame in the most significant byte (MSB). Interface has data width 128 bits.
  • Support for jumbo packets, defined as packets greater than 1500 bytes.
  • Receive (RX) CRC removal and pass-through control.
  • Optional transmit (TX) CRC generation and insertion.
  • RX CRC checking and error reporting.
  • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
  • Optional RX strict SFD checking per IEEE specification.
  • RX malformed packet checking per IEEE specification.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Received control frame type indication.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard
  • Hardware and software reset control.
  • MAC provides RX cut-through frame processing, no RX store-and-forward capability.
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Optional access to Native PHY Debug Master Endpoint (NPDME) for serial link debugging.
  • Programmable ready latency of 0 or 3 clock cycles for Avalon-ST TX interface.
  • Optional statistics counters.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.