4.7. Intel® Stratix® 10 EPE - PLL Worksheet
For Intel® Stratix® 10 devices, the supported PLL types are IOPLL, fPLL, ATX PLL, and CMU PLL.
|Specify a name for the PLL in this column. This is an optional value.
|Specifies the type of PLL. Intel® Stratix® 10 devices have I/O PLLs, fPLLs, CMU PLLs, and ATX PLLs. CMU PLLs and ATX PLLs are for L-tile and H-tile transceiver use exclusively. (E-tile transmitter PLLs are included in the XCVR worksheet and are not included in the PLL worksheet.)
|# PLL Blocks
|Enter the number of PLL blocks with the same combination of parameters.
|XCVR Die ID
|Specify the transceiver die on which PLLs on this row are located. This field is not applicable for I/O PLLs.
|Enter the number of counters of the PLL. For fPLL, this includes C counter, L counter, and feedback. This field is not applicable for ATX PLLs and CMU PLLs.
|VCCR_GXB and VCCT_GXB Voltage
|Specify the voltage of the VCCR_GXB and VCCT_GXB rails. This field is not applicable for I/O PLLs.
|Output Freq (MHz)
|Specify the output frequency for CMU and ATX PLLs.
|VCO Freq (MHz)
|Specify the internal VCO operating frequency for fPLLs and I/O PLLs. When using an fPLL as a transmitter PLL for XCVR channels, the VCO frequency has to be such that the required fPLL output frequency can be achieved using a legal value of the counter used for HSSI clock output.
You can find the VCO frequency (in Hz) in the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter > Plan Stage > HSSI Transmitter PLL > vco_freq for each fPLL instance.
|Total Power (W)
|Shows the total estimated power for this row (in W).
|Enter any comments. This is an optional entry.
For more information about the PLLs available in Intel® Stratix® 10 devices, refer to the Intel® Stratix® 10 Clocking and PLL User Guide.