Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

ID 683175
Date 12/03/2021
Public
Document Table of Contents

4.3. Intel® Stratix® 10 EPE - Logic Worksheet

The Logic worksheet of the Early Power Estimator (EPE) for Intel® Stratix® 10 devices allows you to enter logic resources for all modules in your design.

Figure 8. Logic Worksheet of the Early Power Estimator


Table 7.  Logic Worksheet Information
Input Parameter Description
Module

Specify a name for each module of the design. This is an optional entry.

#Half ALMs

Enter twice the number of Adaptive Logic Modules (ALMs) used in your design, which you can find in the Compilation Report, by selecting Fitter > Place Stage > Resource Usage Summary. For power estimation purposes, the number of ALMs used in your design is the sum of the following values in the Compilation Report:

  • ALMs used for LUT logic and register circuitry
  • ALMs used for LUT logic
  • ALMs used for register circuitry
  • ALMs adjustment for power estimation

The adjustment for power estimation is necessary because some unused ALMs may still consume power due to Fitter optimizations.

# FFs

Enter the number of Primary logic registers, plus Secondary logic registers, plus the number of registers reported as Register control circuitry for power estimation, all of which you can find in the Compilation Report, by selecting Fitter > Place Stage > Resource Usage Summary. This adjustment is necessary because some unused registers may still consume power due to fitter optimizations.

Clock routing power associated with flipflops is calculated separately on the Clock worksheet of the EPE spreadsheet.

Clock Freq (MHz)

Enter a clock frequency (in MHz). This value is limited by the maximum frequency specification for the device family.

Note:
When you import a design from the Intel® Quartus® Prime software, some imported half ALMs and flipflops may have a clock frequency of 0 MHz; this can occur for one of two reasons:
  • The Intel® Quartus® Prime software did not have sufficient information to determine clock frequency due to incomplete clock constraints.
  • The Intel® Quartus® Prime software exported a comma-separated value (.csv) file containing half ALMs where only flipflops are used. Such ALMs are imported as ALMs with clock frequency of 0 MHz, while their flipflops are imported into a separate row with the correct clock frequency.
Toggle %

Enter the average percentage of clock cycles when the block output signals change values. Toggle percentage is multiplied by clock frequency to determine the number of transitions per second. For example, 100 MHz frequency with a 12.5% toggle rate, means that each LUT or flipflop output toggles 12.5 million times per second (100MHz × 12.5%).

The toggle percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a 16-bit counter. Most logic only toggles infrequently; therefore, toggle rates of less than 50% are more realistic. To ensure you do not underestimate the toggle percentage, use a realistic toggle percentage obtained through simulation.

For example, a T flipflop (TFF) with its input tied to VCC has a toggle rate of 100% because its output is changing logic state on every clock cycle. Refer to the 4-Bit Counter Example below for a more detailed analysis.

For any rows containing flip-flops, toggle percentage cannot exceed 100%. A small portion of ALMs in a design may experience glitching that results in toggle percentage exceeding 100% for such ALMs. Enter such ALMs into a separate row with # FFs set to 0.

Routing Factor

Indicates the extent of the routing power of the outputs.

Characteristics that have a large power impact and are captured by this factor include the following:

  • The fanout of the outputs
  • The number of routing resources used
  • The relative power usage of the different types of routing resources used

The default value for this field is typical; the actual value varies between blocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Intel® Quartus® Prime software after compiling your design, because the Intel® Quartus® Prime software has access to detailed placement and routing information.

In the absence of an Intel® Quartus® Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals.

You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design.

Thermal Power (W) - Routing

Indicates the power dissipation due to estimated routing (in W).

Routing power depends on placement and routing, which is a function of design complexity. The values shown are representative of routing power based on observed behavior across more than 100 real-world designs.

Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact routing used in your design.

Thermal Power (W) - Block

Indicates the power dissipation due to internal toggling of the ALMs (in W).

Logic block power is a combination of the function implemented and the relative toggle rates of the various inputs. The EPE spreadsheet uses an estimate based on observed behavior across more than 100 real-world designs.

Use the Intel® Quartus® Prime Power Analyzer for accurate analysis based on the exact synthesis of your design.

Thermal Power (W) - Total

Indicates the estimated power (in W), based on information entered into the EPE spreadsheet. It is equal to the sum of routing power and block power.

User Comments

Enter any comments. This is an optional entry.

Figure 9. 4-Bit Counter Example

The cout0 output of the first TFF has a toggle percentage of 100% because the signal toggles on every clock cycle. The toggle percentage for the cout1 output of the second TFF is 50% because the output toggles every two clock cycles. Similarly, the toggle percentage for the cout2 and cout3 outputs are 25% and 12.5%, respectively. Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 + 12.5)/4 = 46.875%.

For more information about logic block configurations, refer to the Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide.

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