Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

ID 683175
Date 12/03/2021
Public
Document Table of Contents

4.6. Intel® Stratix® 10 EPE - Clock Worksheet

Each row in the Clock worksheet of the Early Power Estimator (EPE) for Intel® Stratix® 10 devices represents a clock network or a separate clock domain.

Intel® Stratix® 10 devices support global, regional, and periphery clock networks. The EPE spreadsheet does not distinguish between global or regional clocks because the difference in power is not significant.

Figure 12. Clock Worksheet of the Early Power Estimator
Table 10.  Clock Worksheet Information
Column Heading Description
Domain Specify a name for the clock domain in this row. This is an optional value.
Clock Freq (MHz) Enter the frequency of the clock domain. This value is limited by the maximum frequency specification for the device family.
Note:

When you import a design from the Intel® Quartus® Prime software, some imported clocks may have a frequency of 0 MHz, due to either of the following reasons:

  • The Intel® Quartus® Prime software did not have sufficient information to determine clock frequency due to incomplete clock constraints.
  • Clock resources were used to route a reset signal, which toggles infrequently, so its frequency is reported as 0 MHz.
Total Fanout

Enter the total number of flipflops, hyper-registers, RAMs, digital signal processing (DSP) blocks, and I/O pins fed by this clock.

Power consumed by MLAB clocks is accounted for in the RAM worksheet; therefore, clock fanout on this worksheet does not include any MLABs driven by this clock domain.

The number of resources driven by every global clock and regional clock signal is reported in the Fan-out column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter and click Place Stage. Select Global & Other Fast Signals Summary and observe the Fan-out value.

Global Enable % Enter the average percentage of time that the entire clock tree is enabled. Each global clock buffer has an enable signal that you can use to dynamically shut down the entire clock tree.
Local Enable %

Enter the average percentage of time that clock enable is high for destination flipflops.

Local clock enables for flipflops in ALMs are promoted to LAB-wide signals. When a given flipflop is disabled, the LAB-wide clock is disabled, cutting clock power and the power for down-stream logic. This worksheet models only the impact on clock tree power.

Utilization Factor

Represents the impact of the clock network configuration on power.

Characteristics that have a large impact on power and are captured by this factor include the following:

  • Whether the network is widely spread out
  • Whether the fanout is small or large
  • The clock settings within each LAB

The default value for this field is typical; the actual value varies between clocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Intel® Quartus® Prime software after compiling your design, because the Intel® Quartus® Prime software has access to detailed placement information.

In the absence of an Intel® Quartus® Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals.

You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design.

Total Power (W) Indicates the total power dissipation due to clock distribution (in W).
User Comments Enter any comments. This is an optional entry.
Note: The Intel® Quartus® Prime Power Analyzer reports LAB clock power as Block Thermal Dynamic Power under Clock Network block type in the Thermal Power Dissipation by Block Type section of the power report. The Early Power Estimator reports LAB clock power in either the Clock or RAM worksheet, depending on whether the LAB is used to implement logic or used as MLAB, respectively.

For more information about the clock networks of Intel® Stratix® 10 devices, refer to the Intel Stratix 10 Clocking and PLL User Guide.

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