Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

ID 683175
Date 12/03/2021
Public
Document Table of Contents

6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.12.03 19.2
  • In the Worksheets chapter, added the Why Typical Power Might Appear Larger than Maximum Power section to the Common Worksheet Elements topic.
2019.07.25 19.2
  • In the Intel® Stratix® 10 EPE - XCVR Worksheet topic:
    • Updated the figure.
    • In the XCVR Worksheet Information table, changed column heading PCS/PMA Interface Width to Digital/Analog Interface Width.
    • In the XCVR Worksheet Information table, added Power Mode row.
    • In the XCVR Worksheet Information table, changed PCS/HIP Mode column heading to Protocol Mode. Updated the corresponding description.
    • Modified the description for the Pre-Emphasis Setting-First Pre-Tap and Pre-Emphasis Setting-First Post-Tap column headings.
2019.03.06 18.1 Changed the E-tile transceiver portion of the description of # of Channels in the XCVR Worksheet Information table, in the Intel® Stratix® 10 EPE – XCVR Worksheet topic.
2018.09.24 18.1
  • Added link from the Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices topic to the Early Power Estimators and Power Analyzer page on the Intel website.
  • Added information to the description of the VCO Freq (MHz) field in the PLL Worksheet Information table.
  • Added link from the Intel® Stratix® 10 EPE - XCVR Worksheet topic to the Intel® Stratix® 10 Transceiver PHY User Guide.
  • In the HPS worksheet description, updated the image and the descriptions in the HPS Worksheet Information table.
  • In the Report worksheet description, added the Power Rail Configuration Settings in the Report Worksheet table. Also updated the image and added descriptions of the Recommended Margin and Regulator Group parameters to the Current and Power Regulator Requirements Per Voltage Rail table.
  • In Appendix A. Measuring Static Power, changed occurrences of TADC to Intel® Stratix® 10 Temperature Sensor IP Core.
2018.07.01 18.0
  • In the Main worksheet description, updated the image. Added Total Power Before SmartVID Savings to the Thermal Power (W) Information table, and added a sentence to the SmartVID Power Savings description.
  • In the Logic worksheet description, modified the #Half ALMs description and modified the # FFs description.
  • In the RAM worksheet description, updated the image.
  • In the I/O worksheet description, updated the image.
  • In the Report worksheet description, updated the image. Added Total Current Before SmartVID Savings (A) to the Current and Power Regulator Requirements Per Voltage Rail table. Modified description of Total Current (A) parameter.
Date Version Changes
November 2017 2017.11.06
  • Added Main_HBMTotalPower to the Main worksheet description.
  • Replaced Bank ID with XCVR Die ID, and added PLL Type to PLL worksheet description.
  • Replaced Bank ID with XCVR Die ID, and modified descriptions of Total Thermal Power, Analog Power, Treatment of Unused HSSI Dies, Application, and Analog Power (W) on the XCVR worksheet.
  • Modified description of Apply Recommended Margin, and added HBM Thermal Power (W), HBM Die ΨJC (oC/W), and FPGA Core TSD Offset (oC) on the Thermal worksheet.
  • Added Intel® Stratix® 10 EPE - Enpirion Worksheet topic.
  • Added Intel® Stratix® 10 EPE - HBM Worksheet topic.
  • Added Power Rail Configuration and Regulator Group to the Reports worksheet description.
  • Updated the images for the Main, PLL, XCVR, HPS, Thermal, and Report worksheets.
March 2017 2017.03.31 Initial release.

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