Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

ID 683175
Date 12/03/2021
Public
Document Table of Contents

1.1. Intel® Stratix® 10 EPE Power Model Status

The power models in the Early Power Estimator (EPE) for Intel® Stratix® 10 devices can be in advance, preliminary, or final status.

Advance power models are based on simulation results, process model projections, and design targets. Preliminary power models include post-layout simulation results, process data, and initial silicon correlation results. Advance and preliminary power models may change over time. Final power models correlate to production devices with thousands of designs, and are not expected to change. The Main worksheet of the EPE spreadsheet shows power model status for the selected device.

The accuracy of the power model is determined on a per-power-rail basis for both the Power Analyzer and the Early Power Estimator. For most designs, the Power Analyzer and the EPE spreadsheet have the following accuracies, with final power models:
  • Power Analyzer: Within 10% of silicon for the majority of power rails and the highest power rails, assuming accurate inputs and toggle rates.
  • EPE spreadsheet: Within 15% of silicon for the majority of power rails and the highest power rails, assuming accurate inputs and toggle rates. Recommended margins are shown in the report tab (see Report tab section).

See Section 5 for information on factors impacting power estimation accuracy.

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