The IP receives the serial data from the Transceiver Native PHY and performs data alignment, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling.

The design stores the EDID information using the RAM 1-port IP core. A standard two-wire (clock and data) serial bus protocol (I²C slave-only controller) transfers the CEA-861-D Compliant E-EDID data structure. This EDID RAM stores the E-EDID information.

The IOPLL generates the RX CDR reference clock, link speed clock, and video clock for the incoming TMDS clock.

• Output clock 0 (CDR reference clock)
• Output clock 1 (Link speed clock)
• Output clock 2 (Video clock)

The Transceiver PHY reset controller ensures a reliable initialization of the RX transceivers. The reset input of this controller is triggered by the RX reconfiguration, and it generates the corresponding analog and digital reset signal to the Transceiver Native PHY block according to the reset sequencing inside the block.

Hard transceiver block that receives the serial data from an external video source. It deserializes the serial data to parallel data before passing the data to the HDMI RX core.

RX reconfiguration management that implements rate detection circuitry with the HDMI PLL to drive the RX transceiver to operate at any arbitrary link rates ranging from 250 Mbps to 6,000 Mbps.

Refer to Figure 23 below.

IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth in real time, without reconfiguring the entire FPGA. This block runs at 100 MHz in Intel® Arria® 10 devices.

Due to IOPLL reconfiguration limitation, apply the Quartus INI permit_nf_pll_reconfig_out_of_lock=on during the IOPLL reconfiguration IP generation.

To apply the Quartus INI, include “permit_nf_pll_reconfig_out_of_lock=on” in the quartus.ini file and place in the file the Intel® Quartus® Prime project directory. You should see a warning message when you edit the IOPLL reconfiguration block (pll_hdmi_reconfig) in the Quartus Prime software with the INI.

The IP core receives video data from the top level and performs TMDS encoding, auxiliary data encoding, audio data encoding, video data encoding, and scrambling.

The IOPLL supplies the link speed clock and video clock from the incoming TMDS clock.

• Output clock 1 (Link speed clock)
• Output clock 2 (Video clock)

The Transceiver PHY reset controller ensures a reliable initialization of the TX transceivers. The reset input of this controller is triggered from the top level, and it generates the corresponding analog and digital reset signal to the Transceiver Native PHY block according to the reset sequencing inside the block.

The tx_ready output signal from this block also functions as a reset signal to the HDMI Intel® FPGA IP to indicate the transceiver is up and running, and ready to receive data from the core.

Hard transceiver block that receives the parallel data from the HDMI TX core and serializes the data from transmitting it.

Reconfiguration interface is enabled in the TX Native PHY block to demonstrate the connection between TX Native PHY and transceiver arbiter. No reconfiguration is performed for TX Native PHY.

The transmitter PLL block provides the serial fast clock to the Transceiver Native PHY block. For this HDMI Intel® FPGA IP design example, fPLL is used as TX PLL.

IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth in real time, without reconfiguring the entire FPGA. This block runs at 100 MHz in Intel® Arria® 10 devices.

Due to IOPLL reconfiguration limitation, apply the Quartus INI permit_nf_pll_reconfig_out_of_lock=on during the IOPLL reconfiguration IP generation.

To apply the Quartus INI, include “permit_nf_pll_reconfig_out_of_lock=on” in the quartus.ini file and place in the file the Intel® Quartus® Prime project directory. You should see a warning message when you edit the IOPLL reconfiguration block (pll_hdmi_reconfig) in the Intel® Quartus® Prime software with the INI.

This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.

This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially.

The interface connection between the transceiver arbiter and TX/RX Native PHY/PHY Reset Controller blocks in this design example demonstrates a generic mode that apply for any IP combination using the transceiver arbiter. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel.

The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.

• The video data output and synchronization signals from HDMI RX core loop through a DCFIFO across the RX and TX video clock domains.
• The General Control Packet (GCP), InfoFrames (AVI, VSI and AI), auxiliary data, and audio data loop through DCFIFOs across the RX and TX link speed clock domains.
• The auxiliary data port of the HDMI TX core controls the auxiliary data that flow through the DCFIFO through backpressure. The backpressure ensures there is no incomplete auxiliary packet on the auxiliary data port.
• This block also performs external filtering:
  • Filters the audio data and audio clock regeneration packet from the auxiliary data stream before transmitting to the HDMI TX core auxiliary data port.
    Note: To disable this filtering, press user_pb[2]. Enable this filtering to ensure there is no duplication of audio data and audio clock regeneration packet in the retransmitted auxiliary data stream.
  • Filters the High Dynamic Range (HDR) InfoFrame from the HDMI RX auxiliary data and inserts an example HDR InfoFrame to the auxiliary data of the HDMI TX through the Avalon ST multiplexer.

The CPU sub-system functions as SCDC and DDC controllers, and source reconfiguration controller.

• The source SCDC controller contains the I²C master controller. The I²C master controller transfers the SCDC data structure from the FPGA source to the external sink for HDMI 2.0b operation. For example, if the outgoing data stream is 6,000 Mbps, the Nios II processor commands the I²C master controller to update the TMDS_BIT_CLOCK_RATIO and SCRAMBLER_ENABLE bits of the sink TMDS configuration register to 1.
• The same I²C master also transfers the DDC data structure (E-EDID) between the HDMI source and external sink.
• The Nios II CPU acts as the reconfiguration controller for the HDMI source. The CPU relies on the periodic rate detection from the RX Reconfiguration Management module to determine if the TX requires reconfiguration. The Avalon-MM slave translator provides the interface between the Nios II processor Avalon-MM master interface and the Avalon-MM slave interfaces of the externally instantiated HDMI source’s IOPLL and TX Native PHY.
• The reconfiguration sequence flow for TX is same as RX, except that the PLL and transceiver reconfiguration and the reset sequence is performed sequentially. Refer to Figure 24.