HDMI Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683156
Date 12/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

2.10. Interface Signals

The tables list the signals for the HDMI design example with FRL enabled.
Table 16.  Top-Level Signals
Signal Direction Width Description
On-board Oscillator Signal
clk_fpga_b3_p

Input

 1

100 MHz free running clock for core reference clock.

refclk4_p

Input

 1

100 MHz free running clock for transceiver reference clock.
User Push Buttons and LEDs
user_pb

Input

 3

Push button to control the HDMI Intel® FPGA IP design functionality.

cpu_resetn

Input

 1

Global reset.
user_led_g

Output

 8

Green LED display.

Refer to Hardware Setup for more information about the LED functions.

user_dipsw

Input

 1

User-defined DIP switch.

Refer to Hardware Setup for more information about the DIP switch functions.

HDMI FMC Daughter Card Pins on FMC Port B
fmcb_gbtclk_m2c_p_0

Input

1

 HDMI RX TMDS clock.
fmcb_dp_m2c_p

Input

 4

HDMI RX clock, red, green, and blue data channels.
fmcb_dp_c2m_p

Output

 4

HDMI TX clock, red, green, and blue data channels.
fmcb_la_rx_p_9

Input

 1

HDMI RX +5V power detect.
fmcb_la_rx_p_8

Output

 1 HDMI RX hot plug detect.
fmcb_la_rx_n_8

Input

 1

HDMI RX I2C SDA for DDC and SCDC.

fmcb_la_tx_p_10

Input

 1 HDMI RX I2C SCL for DDC and SCDC.
fmcb_la_tx_p_12

Input

 1 HDMI TX hot plug detect.
fmcb_la_tx_n_12

Input

 1 HDMI I2C SDA for DDC and SCDC.
fmcb_la_rx_p_10

Input

 1

HDMI I2C SCL for DDC and SCDC.

fmcb_la_tx_n_9

Input

 1

HDMI I2C SDA for redriver control.

fmcb_la_rx_p_11

Input

 1

HDMI I2C SCL for redriver control.

fmcb_la_tx_n_13 Output 1 HDMI TX +5V
Note: Only available when Bitec HDMI Daughter Card Revision 9 is selected.
Table 17.  HDMI RX Top-Level Signals
Signal Direction Width Description
Clock and Reset Signals
mgmt_clk

Input

 1

System clock input (100 MHz).
reset

Input

 1

System reset input.
rx_tmds_clk

Input

 1

HDMI RX TMDS clock.
i2c_clk

Input

 1

Clock input for DDC and SCDC interface.
rxphy_cdr_refclk1

Input

 1

Clock input for RX CDR reference clock 1. The clock frequency is 100 MHz.

rx_vid_clk

Output

 1

Video clock output.
sys_init

Output

 1

System initialization to reset the system upon power-up.
RX Transceiver and IOPLL Signals
rxpll_tmds_locked

Output

 1

Indicates the TMDS clock IOPLL is locked.
rxpll_frl_locked

Output

 1

Indicates the FRL clock IOPLL is locked.
rxphy_serial_data

Input

 4

HDMI serial data to the RX Native PHY.
rxphy_ready

Output

 1

Indicates the RX Native PHY is ready.
rxphy_cal_busy_raw

Output

 4

RX Native PHY calibration busy to the transceiver arbiter.
rxphy_cal_busy_gated

Input

 4

Calibration busy signal from the transceiver arbiter to the RX Native PHY.

rxphy_rcfg_slave_write

Input

 4

Transceiver reconfiguration Avalon® memory-mapped interface from the RX Native PHY to the transceiver arbiter.

rxphy_rcfg_slave_read

Input

 4
rxphy_rcfg_slave_address

Input

 40
rxphy_rcfg_slave_writedata

Input

 128
rxphy_rcfg_slave_readdata

Output

 128
rxphy_rcfg_slave_waitrequest

Output

 4
RX Reconfiguration Management
rxphy_rcfg_busy

Output

 1

RX Reconfiguration busy signal.
rx_tmds_freq

Output

 24

HDMI RX TMDS clock frequency measurement (in 10 ms).
rx_tmds_freq_valid

Output

 1

Indicates the RX TMDS clock frequency measurement is valid.
rxphy_os

Output

 1
Oversampling factor:
  • 0: 1x oversampling
  • 1: 5× oversampling
rxphy_rcfg_master_write

Output

 1

RX reconfiguration management Avalon® memory-mapped interface to transceiver arbiter.

rxphy_rcfg_master_read

Output

 1
rxphy_rcfg_master_address

Output

 12
rxphy_rcfg_master_writedata

Output

 32
rxphy_rcfg_master_readdata

Input

 32
rxphy_rcfg_master_waitrequest

Input

 1
HDMI RX Core Signals
rx_vid_clk_locked

Input

 1

Indicates vid_clk is stable.
rxcore_frl_rate

Output

 4

Indicates the FRL rate that the RX core is running.

  • 0: Legacy Mode (TMDS)
  • 1: 3 Gbps 3 lanes
  • 2: 6 Gbps 4 lanes
  • 3: 6 Gbps 4 lanes
  • 4: 8 Gbps 4 lanes
  • 5: 10 Gbps 4 lanes
  • 6: 12 Gbps 4 lanes
  • 7-15: Reserved
rxcore_frl_locked

Output

 4

Each bit indicates the specific lane that has achieved FRL lock. FRL is locked when the RX core successfully performs alignment, deskew, and achieves lane lock.

  • For 3-lane mode, lane lock is achieved when the RX core receives Scrambler Reset (SR) or Start-Super-Block (SSB) for every 680 FRL character periods for at least 3 times.
  • For 4-lane mode, lane lock is achieved when the RX core receives Scrambler Reset (SR) or Start-Super-Block (SSB) for every 510 FRL character periods for at least 3 times.
rxcore_frl_ffe_levels

Output

 4 Corresponds to the FFE_level bit in the SCDC 0x31 register bit [7:4] in the RX core.
rxcore_frl_flt_ready

Input

 1 Asserts to indicate the RX is ready for the link training process to start. When asserted, the FLT_ready bit in the SCDC register 0x40 bit 6 is asserted as well.
rxcore_frl_src_test_config

Input

 8 Specifies the source test configurations. The value is written into the SCDC Test Configuration register in the SCDC register 0x35.
rxcore_tbcr

Output

 1

Indicates the TMDS bit to clock ratio; corresponds to the TMDS_Bit_Clock_Ratio register in the SCDC register 0x20 bit 1.

  • When running in HDMI 2.0 mode, this bit is asserted. Indicates the TMDS bit to clock ratio of 40:1.
  • When running in HDMI 1.4b, this bit is not asserted. Indicates the TMDS bit to clock ratio of 10:1.
  • This bit is unused for FRL mode.
rxcore_scrambler_enable

Output

 1 Indicates if the received data is scrambled; corresponds to the Scrambling_Enable field in the SCDC register 0x20 bit 0.
rxcore_audio_de

Output

 1

HDMI RX core audio interfaces

Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

rxcore_audio_data

Output

 256
rxcore_audio_info_ai

Output

 48
rxcore_audio_N

Output

 20
rxcore_audio_CTS

Output

 20
rxcore_audio_metadata

Output

 165
rxcore_audio_format

Output

 5
rxcore_aux_pkt_data

Output

 72

HDMI RX core auxiliary interfaces

Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

rxcore_aux_pkt_addr

Output

 6
rxcore_aux_pkt_wr

Output

 1
rxcore_aux_data

Output

 72
rxcore_aux_sop

Output

 1
rxcore_aux_eop

Output

 1
rxcore_aux_valid

Output

 1
rxcore_aux_error

Output

 1
rxcore_gcp

Output

 6

HDMI RX core sideband signals

Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

rxcore_info_avi

Output

 123
rxcore_info_vsi

Output

 61
rxcore_locked

Output

 1

HDMI RX core video ports

Note: N = pixels per clock

Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

rxcore_vid_data

Output

 N*48
rxcore_vid_vsync

Output

 N
rxcore_vid_hsync

Output

 N
rxcore_vid_de

Output

 N
rxcore_vid_valid

Output

 1
rxcore_vid_lock

Output

 1
rxcore_mode

Output

 1

HDMI RX core control and status ports.

Note: N = symbols per clock

Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

rxcore_ctrl

Output

 N*6
rxcore_color_depth_sync

Output

 2
hdmi_5v_detect

Input

 1

HDMI RX 5V detect and hotplug detect.

Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

hdmi_rx_hpd

Output

 1
rx_hpd_trigger

Input

 1
I2C Signals
hdmi_rx_i2c_sda

Input

 1

HDMI RX DDC and SCDC interface.
hdmi_rx_i2c_scl

Input

 1
RX EDID RAM Signals
edid_ram_access

Input

 1

HDMI RX EDID RAM access interface.

Assert edid_ram_access when you want to write or read from the EDID RAM, else this signal should be kept low.

When you assert edid_ram_access, the hotplug signal deasserts to allow write or read to the EDID RAM. When EDID RAM access is completed, you should deassert edid_ram_assess and the hotplug signal asserts. The source will read the new EDID due to the hotplug signal toggling.

edid_ram_address

Input

 8
edid_ram_write

Input

 1
edid_ram_read

Input

 1
edid_ram_readdata

Output

 8
edid_ram_writedata

Input

 8
edid_ram_waitrequest

Output

 1
Table 18.  HDMI TX Top-Level Signals
Signal Direction Width Description
Clock and Reset Signals
mgmt_clk

Input

 1

System clock input (100 MHz).
reset

Input

 1

System reset input.

tx_tmds_clk

Input

 1

HDMI RX TMDS clock.
txfpll_refclk1

Input

 1

Clock input for TX PLL reference clock 1. The clock frequency is 100 MHz.

tx_vid_clk

Output

 1

Video clock output.
tx_frl_clk

Output

 1

FRL clock output.
sys_init

Input

 1

System initialization to reset the system upon power-up.

tx_init_done

Input

 1

TX initialization to reset the TX reconfiguration management block and transceiver reconfiguration interface.

TX Transceiver and IOPLL Signals
txpll_frl_locked

Output

 1

Indicates the link speed clock and FRL clock IOPLL is locked.

txfpll_locked

Output

 1

Indicates the TX PLL is locked.
txphy_serial_data

Output

 4

HDMI serial data from the TX Native PHY.
txphy_ready

Output

 1

Indicates the TX Native PHY is ready.
txphy_cal_busy

Output

 1

TX Native PHY calibration busy signal.
txphy_cal_busy_raw

Output

 4

Calibration busy signal to the transceiver arbiter.

txphy_cal_busy_gated

Input

 4

Calibration busy signal from the transceiver arbiter to the TX Native PHY.

txphy_rcfg_busy

Output

 1

Indicates the TX PHY reconfiguration is in progress.

txphy_rcfg_slave_write

Input

 4

Transceiver reconfiguration Avalon® memory-mapped interface from the TX Native PHY to the transceiver arbiter.

txphy_rcfg_slave_read

Input

 4
txphy_rcfg_slave_address

Input

40
txphy_rcfg_slave_writedata

Input

 128
txphy_rcfg_slave_readdata

Output

 128
txphy_rcfg_slave_waitrequest

Output

 4
TX Reconfiguration Management
tx_tmds_freq

Input

 24

HDMI TX TMDS clock frequency value (in 10 ms).

tx_os

Output

 2
Oversampling factor:
  • 0: 1x oversampling
  • 1: 2× oversampling
  • 2: 8x oversampling
txphy_rcfg_master_write

Output

 1

TX reconfiguration management Avalon® memory-mapped interface to transceiver arbiter.

txphy_rcfg_master_read

Output

 1
txphy_rcfg_master_address

Output

 12
txphy_rcfg_master_writedata

Output

 32
txphy_rcfg_master_readdata

Input

 32
txphy_rcfg_master_waitrequest

Input

 1
tx_reconfig_done Output 1

Indicates that the TX reconfiguration process is completed.

HDMI TX Core Signals
tx_vid_clk_locked

Input

 1

Indicates vid_clk is stable.

txcore_ctrl

Input

 N*6

HDMI TX core control interfaces.

Note: N = pixels per clock

Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

txcore_mode

Input

 1
txcore_audio_de

Input

 1

HDMI TX core audio interfaces.

Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

txcore_audio_mute Input 1
txcore_audio_data

Input

 256
txcore_audio_info_ai

Input

 49
txcore_audio_N

Input

 20
txcore_audio_CTS

Input

 20
txcore_audio_metadata

Input

 166
txcore_audio_format

Input

 5
txcore_aux_ready

Output

 1

HDMI TX core auxiliary interfaces.

Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

txcore_aux_data

Input

 72
txcore_aux_sop

Input

 1
txcore_aux_eop

Input

 1
txcore_aux_valid

Input

 1
txcore_gcp

Input

 6

HDMI TX core sideband signals.

Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

txcore_info_avi

Input

 123
txcore_info_vsi

Input

 62
txcore_i2c_master_write

Input

 1

TX I2C master Avalon® memory-mapped interface to I2C master inside the TX core.

Note: These signals are available only when you turn on the Include I2C parameter.
txcore_i2c_master_read

Input

 1
txcore_i2c_master_address

Input

 4
txcore_i2c_master_writedata

Input

 32
txcore_i2c_master_readdata

Output

 32
txcore_vid_data

Input

 N*48

HDMI TX core video ports.

Note: N = pixels per clock

Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information.

txcore_vid_vsync

Input

 N
txcore_vid_hsync

Input

 N
txcore_vid_de

Input

 N
txcore_vid_ready Output 1
txcore_vid_overflow Output 1
txcore_vid_valid Input 1
txcore_frl_rate Input 4

SCDC register interfaces.
txcore_frl_pattern Input 16
txcore_frl_start Input 1
txcore_scrambler_enable Input 1
txcore_tbcr Input 1
I2C Signals
nios_tx_i2c_sda_in

Output

 1

TX I2C Master interface for SCDC and DDC from the Nios® II processor to the output buffer.

Note: If you turn on the Include I2C parameter, these signals will be placed inside the TX core and will not be visible at this level.
nios_tx_i2c_scl_in

Output

 1
nios_tx_i2c_sda_oe

Input

 1
nios_tx_i2c_scl_oe

Input

 1
nios_ti_i2c_sda_in

Output

 1

TX I2C Master interface from the Nios® II processor to the output buffer to control TI redriver on the Bitec HDMI 2.1 FMC daughter card.

nios_ti_i2c_scl_in

Output

 1
nios_ti_i2c_sda_oe

Input

 1
nios_ti_i2c_scl_oe Input 1
hdmi_tx_i2c_sda

Input

 1

TX I2C interfaces for SCDC and DDC interfaces from the output buffer to the HDMI TX connector.

hdmi_tx_i2c_scl

Input

 1
hdmi_tx_ti_i2c_sda Input 1

TX I2C interfaces from the output buffer to the TI redriver on the Bitec HDMI 2.1 FMC daughter card.

hdmi_tx_ti_i2c_scl Input 1
Hotplug Detect Signals
tx_hpd_req

Output

 1 HDMI TX hotplug detect interfaces.
hdmi_tx_hpd_n

Input

 1
Table 19.  Transceiver Arbiter Signals
Signal Direction Width Description
clk

Input

 1

Reconfiguration clock. This clock must share the same clock with the reconfiguration management blocks.

reset

Input

 1

Reset signal. This reset must share the same reset with the reconfiguration management blocks.

rx_rcfg_en

Input

 1

RX reconfiguration enable signal.
tx_rcfg_en

Input

 1

TX reconfiguration enable signal.
rx_rcfg_ch

Input

 2

Indicates which channel to be reconfigured on the RX core. This signal must always remain asserted.

tx_rcfg_ch

Input

 2

Indicates which channel to be reconfigured on the TX core. This signal must always remain asserted.

rx_reconfig_mgmt_write

Input

 1

Reconfiguration Avalon® memory-mapped interfaces from the RX reconfiguration management.

rx_reconfig_mgmt_read

Input

 1
rx_reconfig_mgmt_address

Input

10
rx_reconfig_mgmt_writedata

Input

 32
rx_reconfig_mgmt_readdata

Output

 32
rx_reconfig_mgmt_waitrequest

Output

 1
tx_reconfig_mgmt_write

Input

 1

Reconfiguration Avalon® memory-mapped interfaces from the TX reconfiguration management.

tx_reconfig_mgmt_read

Input

 1
tx_reconfig_mgmt_address

Input

10
tx_reconfig_mgmt_writedata

Input

 32
tx_reconfig_mgmt_readdata

Output

 32
tx_reconfig_mgmt_waitrequest

Output

 1
reconfig_write

Output

 1

Reconfiguration Avalon® memory-mapped interfaces to the transceiver.

reconfig_read

Output

 1
reconfig_address

Output

10
reconfig_writedata

Output

 32
rx_reconfig_readdata

Input

 32
rx_reconfig_waitrequest

Input

 1
tx_reconfig_readdata

Input

 1
tx_reconfig_waitrequest

Input

 1
rx_cal_busy

Input

 1

Calibration status signal from the RX transceiver.
tx_cal_busy

Input

 1

Calibration status signal from the TX transceiver.
rx_reconfig_cal_busy

Output

 1

Calibration status signal to the RX transceiver PHY reset control.
tx_reconfig_cal_busy

Output

 1

Calibration status signal from the TX transceiver PHY reset control.

Table 20.  RX-TX Link Signals
Signal Direction Width Description
vid_clk

Input

 1

HDMI video clock.
rx_vid_lock

Input

 3

Indicates HDMI RX video lock status.

rx_vid_valid

Input

 1 HDMI RX video interfaces.
rx_vid_de

Input

 N
rx_vid_hsync

Input

 N
rx_vid_vsync

Input

 N
rx_vid_data

Input

 N*48
rx_aux_eop

Input

 1

HDMI RX auxiliary interfaces.
rx_aux_sop

Input

 1
rx_aux_valid

Input

 1
rx_aux_data

Input

 72
tx_vid_de

Output

 N

HDMI TX video interfaces.

Note: N = pixels per clock
tx_vid_hsync

Output

 N
tx_vid_vsync

Output

 N
tx_vid_data

Output

 N*48
tx_vid_valid

Output

 1
tx_vid_ready

Input

 1
tx_aux_eop

Output

 1

HDMI TX auxiliary interfaces.
tx_aux_sop

Output

 1
tx_aux_valid

Output

 1
tx_aux_data

Output

 72
tx_aux_ready

Input

 1
Table 21.   Platform Designer System Signals
Signal Direction Width Description
cpu_clk_in_clk_clk

Input

 1

CPU clock.
cpu_rst_in_reset_reset

Input

 1

CPU reset.
edid_ram_slave_translator_avalon_anti_slave_0_address

Output

 8

EDID RAM access interfaces.

edid_ram_slave_translator_avalon_anti_slave_0_write

Output

 1
edid_ram_slave_translator_avalon_anti_slave_0_read

Output

 1
edid_ram_slave_translator_avalon_anti_slave_0_readdata

Input

 8
edid_ram_slave_translator_avalon_anti_slave_0_writedata

Output

 8
edid_ram_slave_translator_avalon_anti_slave_0_waitrequest

Input

 1
hdmi_i2c_master_i2c_serial_sda_in

Input

 1

I2C Master interfaces from the Nios® II processor to the output buffer for DDC and SCDC control.

hdmi_i2c_master_i2c_serial_scl_in

Input

 1
hdmi_i2c_master_i2c_serial_sda_oe

Output

 1
hdmi_i2c_master_i2c_serial_scl_oe

Output

 1
redriver_i2c_master_i2c_serial_sda_in

Input

 1 I2C Master interfaces from the Nios® II processor to the output buffer for TI redriver setting configuration.
redriver_i2c_master_i2c_serial_scl_in

Input

 1
redriver_i2c_master_i2c_serial_sda_oe

Output

 1
redriver_i2c_master_i2c_serial_scl_oe

Output

 1
pio_in0_external_connection_export

Input

 32

Parallel input output interfaces.

  • Bit 0: Connected to the user_dipsw signal to control EDID passthrough mode.
  • Bit 1: TX HPD request
  • Bit 2: TX transceiver ready
  • Bits 3: TX reconfiguration done
  • Bits 4–7: Reserved
  • Bits 8–11: RX FRL rate
  • Bit 12: RX TMDS bit clock ratio
  • Bits 13–16: RX FRL locked
  • Bits 17–20: RX FFE levels
  • Bit 21: RX alignment locked
  • Bit 22: RX video lock
  • Bit 23: User push button 2 to read SCDC registers from external sink
  • Bits 24–31: Reserved
pio_out0_external_connection_export

Output

 32

Parallel input output interfaces.

  • Bit 0: TX HPD acknowledgment
  • Bit 1: TX initialization is done
  • Bits 2–7: Reserved
  • Bits 8–11: TX FRL rate
  • Bits 12–27: TX FRL link training pattern
  • Bit 28: TX FRL start
  • Bits 29–31: Reserved
pio_out1_external_connection_export

Output

 32

Parallel input output interfaces.

  • Bit 0: RX EDID RAM access
  • Bit 1: RX FLT ready
  • Bits 2–7: Reserved
  • Bits 8–15: RX FRL source test configuration
  • Bits 16–31: Reserved
Level Two Title

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