Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

ID 683147
Date 12/14/2020

1.2. Simulation Design Example Components

Figure 3.  Low Latency 50G Ethernet Simulation Design Example Block Diagram
Table 1.   Low Latency 50G Ethernet Core Testbench File Descriptions

File Names


Key Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts


The Mentor Graphics* ModelSim* script to run the testbench.


The Synopsys* VCS* script to run the testbench.


The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.


The Cadence NCSim script to run the testbench.

run_xcelium.sh The Cadence Xcelium* script to run the testbench.

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