Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

ID 683147
Date 12/14/2020
Public

1.3. Hardware Design Example Components

Figure 4.  Low Latency 50G Ethernet Hardware Design Example High Level Block Diagram
The Low Latency 50G Ethernet hardware design example includes the following components:
  • Low Latency 50G Ethernet IP core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • One ATX PLL and one clock buffer to drive the device transceiver channels.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.

The hardware design example uses run_test command to initiate packet transmission from packet generator to the IP core. Use the loop_on command to turn on internal serial loopback for this design example. If the internal serial loopback is turned on, the IP core receives the packets and transmit to the packet generator. The MAC checks the received packets and updates the statistic counters. Use the chkmac_stats command in the system console to read and print out the MAC statistic registers once the packet transmissions completed.

Table 2.   Low Latency 50G Ethernet Core Hardware Design Example File Descriptions

File Names

Description

alt_e50s10.qpf Intel® Quartus® Prime project file
alt_e50s10.qsf Intel® Quartus® Prime project settings file
alt_e50s10.sdc, alt_e50s10_clock.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Low Latency 50G Ethernet design.
alt_e50s10.v Top-level Verilog HDL design example file
common/ Hardware design example support files
hwtest/main.tcl

Main file for accessing System Console

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