Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

ID 683147
Date 12/14/2020
Public

2.4. Design Example Registers

Table 5.   Low Latency 50G Ethernet Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console.
Word Offset Register Type
0x300-0x3FF PHY registers
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x600-0x7FF Flow Control registers
0x0800–0x08FF TX statistics counters
0x0900–0x09FF RX statistics counters
0x1000 Packet Client registers
0x4000 PMA registers1
Table 6.  Packet Client Registers You can customize the Low Latency 50G Ethernet hardware design example by programming the packet client registers.
Address Name Bit Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string "CLNT" RO
0x1006 PKT_CL_TSD [7:0] Intel® Stratix® 10 device temperature sensor diode readout in Fahrenheit. RO
0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit [29:16]: Specify the upper limit of the packet size in bytes. This is only applicable to incremental mode.
  • Bit [13:0]:
    • For fixed mode, these bits specify the transmit packet size in bytes.
    • For incremental mode, these bits specify the lower limit of the transmit packet size in bytes.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit [31]:
    • 1: For fixed/incremental mode with fixed number of packets, this is the number of packets enable bit.
    • 0: For random mode or fixed/incremental mode without fixed number of packets.
  • Bits [30:0]:
    • If bit [31] is set, specifies the number of packets to be sent by the packet generator.

For more information, refer to the Packet Generator Programming Sequence.

0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator status control bit.
    • 0: Packet generator starts sending out the packets.
    • 1: Packet generator stops sending out the packets.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Random mode
    • 01: Fixed mode
    • 10: Incremental mode
  • Bit [6]:
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
  • Bit [7]: Reserved.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits) 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits) 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits) 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits) 0x8765 RW
0x1015 PKT_CL_LOOPBACK_FIFO_ERR_CLR [2:0] Reports MAC loopback errors.
  • Bit [0]: FIFO underflow. Has the value of 1 if the FIFO has underflowed. This bit is sticky. Has the value of 0 if the FIFO has not underflowed.
  • Bit [1]: FIFO overflow. Has the value of if the FIFO has overflowed. This bit is sticky. Has the value of 0 if the FIFO has not overflowed.
  • Bit [2]: Assert this bit to clear bits [0] and [1].
3'b0 RO
0x1016 PKT_CL_LOOPBACK_RESET [0] MAC loopback reset. Set to the value of 1 to reset the design example MAC loopback. 1'b0 RW
1 Each PHY channel has its PMA registers set. PMA registers sets are offset from each other by 0x800 channel offset, starting at the 0x4000 word offset.

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