Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices
ID
683147
Date
12/14/2020
Public
1.1. Directory Structure
Figure 2. Low Latency 50G Ethernet Design Example Directory Structure
The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design. The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench. The compilation-only design example is located in <design_example_dir>/compilation_test_design.