Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide: For Intel® Stratix® 10 Devices

ID 683147
Date 12/14/2020
Public

3. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP version Changes
2020.12.14 20.4 1.0.0 Initial release.

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