- Standard CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
- Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
- RX CRC checking and error reporting.
- TX error insertion capability to transmit error frame at the end of a packet cycle.
- Hardware and software reset control.
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