Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 6/21/2022
Public

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4.4.1. I/O Assignment Validation Rules

I/O Assignment Analysis validates your assignments against the following rules:

Table 28.  Examples of I/O Rule Checks
Rule Description HDL Required?

I/O bank capacity

Checks the number of pins assigned to an I/O bank against the number of pins allowed in the I/O bank.

No

I/O bank VCCIO voltage compatibility

Checks that no more than one VCCIO is required for the pins assigned to the I/O bank.

No

I/O bank VREF voltage compatibility

Checks that no more than one VREF is required for the pins assigned to the I/O bank.

No

I/O standard and location conflicts

Checks whether the pin location supports the assigned I/O standard.

No

I/O standard and signal direction conflicts

Checks whether the pin location supports the assigned I/O standard and direction. For example, certain I/O standards on a particular pin location can only support output pins.

No

Differential I/O standards cannot have open drain turned on

Checks that open drain is turned off for all pins with a differential I/O standard.

No

I/O standard and drive strength conflicts

Checks whether the drive strength assignments are within the specifications of the I/O standard.

No

Drive strength and location conflicts

Checks whether the pin location supports the assigned drive strength.

No

BUSHOLD and location conflicts

Checks whether the pin location supports BUSHOLD. For example, dedicated clock pins do not support BUSHOLD.

No

WEAK_PULLUP and location conflicts

Checks whether the pin location supports WEAK_PULLUP (for example, dedicated clock pins do not support WEAK_PULLUP).

No

Electromigration check

Checks whether combined drive strength of consecutive pads exceeds a certain limit. For example, the total current drive for 10 consecutive pads on a Stratix® II device cannot exceed 200 mA.

No

PCI_IO clamp diode, location, and I/O standard conflicts

Checks whether the pin location along with the I/O standard assigned supports PCI_IO clamp diode.

No

SERDES and I/O pin location compatibility check

Checks that all pins connected to a SERDES in your design are assigned to dedicated SERDES pin locations.

Yes

PLL and I/O pin location compatibility check

Checks whether pins connected to a PLL are assigned to the dedicated PLL pin locations.

Yes
Table 29.  Signal Switching Noise Rules
Rule Description HDL Required?

I/O bank cannot have single-ended I/O when DPA exists

Checks that no single-ended I/O pin exists in the same I/O bank as a DPA.

No

A PLL I/O bank does not support both a single-ended I/O and a differential signal simultaneously

Checks that there are no single-ended I/O pins present in the PLL I/O Bank when a differential signal exists.

No

Single-ended output is required to be a certain distance away from a differential I/O pin

Checks whether single-ended output pins are a certain distance away from a differential I/O pin.

No

Single-ended output must be a certain distance away from a VREF pad

Checks whether single-ended output pins are a certain distance away from a VREF pad.

No

Single-ended input is required to be a certain distance away from a differential I/O pin

Checks whether single-ended input pins are a certain distance away from a differential I/O pin.

No

Too many outputs or bidirectional pins in a VREFGROUP when a VREF is used

Checks that there are no more than a certain number of outputs or bidirectional pins in a VREFGROUP when a VREF is used.

No

Too many outputs in a VREFGROUP

Checks whether too many outputs are in a VREFGROUP.

No

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