Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 6/21/2022

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Document Table of Contents Adjust Constraints with the Chip Planner

With the Chip Planner you can adjust existing assignments to device resources, such as pins, logic cells, and LABs in a graphical representation of the device floorplan. You can also view equations and routing information and demote assignments by dragging and dropping to Logic Lock regions in the Logic Lock Regions Window.

Figure 4. Chip Planner GUI