Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 6/21/2022
Public

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3.2.2.4.1. Placing IP Components

To place IP components and create a tile plan, follow these steps:
Note: For placing multi-rate IP components, refer to Constraining Dynamic Reconfiguration IP.
  1. Update the plan with existing assignments, as Step 3: Update Plan with Project Assignments describes.
  2. In Tile Interface Planner, click the Plan tab. Tile Interface Planner displays the Design Element hierarchy, alongside a graphical representation of the tile chip or package view.
  3. In the Design Element list, locate the tile interface IP that you want to place. You can search and filter the list by name, IP, placement status, I/Os, and other criteria.
    Figure 30. Unplaced PCIe Tile Interface IP in Plan Tab
  4. To customize design element color coding, double-click a color in the Highlight column to specify a new color.
  5. Use any of the following methods to locate legal tile placements for component IP:
    • In the Design Element list, right-click the tile interface IP that you want to place, and then click Generate Legal Locations for Selected Element.
      Note: You can select multiple IP targeting the same tile to generate legal locations for all IP at once.
    • Click the button next to the Design Element to display a list of Legal Locations.
    Figure 31. Listing Legal Locations for Tile Placement
  6. In Legal Locations, click any location in the list to highlight the location in the floorplan.
    Figure 32. Highlighting Legal Locations for Tile Placement
  7. Double-click any location in Legal Locations to place the element in a legal location. Tile Interface Planner places the IP in the legal location on the device tile, as indicated by color highlighting in the Chip View. When listing legal locations for multiple IPs at once, you can also place multiple IPs at once.
    Figure 33. IP Placed In Legal Tile Location

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