F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/27/2023

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7.6.2. ebfm_barwr_imm Procedure

The ebfm_barwr_imm procedure writes up to four bytes of data to an offset from the specified Endpoint BAR.




ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data, byte_len, tclass)



Address of the Endpoint bar_table structure in BFM shared memory. The bar_table structure stores the address assigned to each BAR so that the driver code does not need to be aware of the actual assigned addresses only the application specific offsets from the BAR.


Number of the BAR used with pcie_offset to determine PCI Express address.


Address offset from the BAR base.


Data to be written. In Verilog HDL, this argument is reg [31:0].In both languages, the bits written depend on the length as follows:

Length Bits Written

  • 4: 31 down to 0
  • 3: 23 down to 0
  • 2: 15 down to 0
  • 1: 7 down to 0

Length of the data to be written in bytes. Maximum length is 4 bytes.


Traffic class to be used for the PCI Express transaction.