F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/27/2023

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Document Table of Contents

4.2.5. Configuration TLP

The F-Tile AVST IP forwards any received Type0/1 Configuration TLP to the Avalon-ST RX streaming interface. User logic has the responsibility to respond with a Completion TLP with a Completion code of Successful Completion (SC), Unsupported Request (UR), Configuration Request Retry Status (CRS), or Completer Abort (CA).

If a Configuration TLP needs to update a register in the PCIe configuration space in the F-Tile PCIe Hard IP, you need to use the User Avalon-MM/Hard IP Reconfiguration interface. The application needs to prevent link programming side effects such as writing into low-power states before sending the Completion associated with the request.

The application logic can check the TX FIFO empty flag in the tx_cdts_limit_o after the Completion enters the TX streaming interface to confirm that the TLP has been sent. For more information on the User Avalon-MM interface, refer to Hard IP Reconfiguration Interface.

Figure 52. Configuration TLP Received by F-Tile AVST IP for PCIe Targeting the Hard IP Internal Registers