F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/27/2023
Document Table of Contents

3.3.5. Completion Buffer Size

F-Tile Avalon-ST IP for PCI Express implements Completion Buffers for Header and Data for each PCIe core/port. In Endpoint mode, when Completion credits are infinite and your application must manage the number of outstanding requests according to the buffer size to prevent overflow and lost of Completion packets.

Table 15.  Completion Buffer Size
Completion Buffer Depth Width (in bits)
Port 0 Completion Header 1144 128
Port 0 Completion Data 1444 256
Port 1 Completion Header 572 128
Port 1 Completion Data 1444 128
Port 2 Completion Header 286 128
Port 2 Completion Data 1444 64
Port 3 Completion Header 286 128
Port 3 Completion Data 1444 64

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